Why does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 LiteWhy does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Why does Nios® V processor simulation fail when using the generated VHDL testbench from Platform Designer?
Description Due to a problem in the Quartus ® Prime Standard Edition software version 25.1, Nios ® V processor simulation may fail with the generated VHDL testbench system from Platform Designer for any processor design. This problem affects: All Altera ® FPGA device families in Quartus ® Prime Standard Edition software, and All Nios ® V processor variants (Nios ® V/g, Nios ® V/m, and Nios ® V/c processors). It is because the generation of the Nios ® V processor VHDL testbench system is not supported in Quartus ® Prime Standard Edition software version 25.1. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, please select “Verilog” at the “Create testbench simulation model” input option. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition software. Related Articles 3.3.1. Preparing Hardware Design for SimulationWhy does Ashling* RiscFree* IDE for Altera® FPGAs detect Core 0 only in a Nios® V processor multicore system?
Description Due to a problem in the Ashling* RiscFree* IDE for Altera software version 25.2.1 (version dated 9 th May 2025), the Ashling* RiscFree* IDE might fail to detect other Nios ® V processor cores (except Core 0) for Nios ® V processor multicore designs. This is because there is a bug in the Ashling* GDBServer software. Error message: [GDB server output] Error: The device configuration selected has only 1 core (Core 0). Core 1 is not available. Resolution To workaround this issue, please switch from Ashling* GDBServer to Open On-Chip Debugger (OpenOCD) when debugging a Nios ® V multicore processor system. Add the “–o" argument when running niosv-download. niosv-download app.elf -o <options> The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.
Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IPWhy does Design Space Explorer only show two effort levels for performance optimization?
Description Due to a problem in the Quartus® II software version 12.0 SP2 and earlier, Design Space Explorer (DSE) may only show two available effort levels when optimizing for performance. There should be five available effort levels. This problem affects designs targeting Arria® V, Cyclone® IV, and Cyclone V devices. Resolution To fix this problem, download and install patch 2.19 from the links below. For designs targeting Arria V or Cyclone V devices, this fix is also included in device patch 2.dp3 or later from the related solution below. You must install the Quartus II software version 12.0 SP2 before installing either of these patches. Download the version 12.0 SP2 patch 2.19 for Windows (.exe) Download the version 12.0 SP2 patch 2.19 for Linux (.tar) Download the Readme for the Quartus II software version 12.0 SP2 patch 2.19 (.txt) This problem is fixed beginning with the Quartus II software version 12.1. Related Articles How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 12.0 SP2?Error: pcie_hard_ip_0_pcie_bfm_0: add_fileset_file: No such file
Description During Qsys system generation, the following error message appears if either of the following conditions are true: 1) The Quartus® II installation does not include the Stratix® IV device family and your design is targeting a Cyclone® IV GX device. 2) You are using the Quartus® II Web Edition to generate the testbench. Error: pcie_hard_ip_0_pcie_bfm_0: add_fileset_file: No such file <Quartus II install directory>/eda/sim_lib/stratixiv_hssi_atoms.v while executing "add_fileset_file altpcietb_bfm_driver.v VERILOG PATH /eda/sim_lib/stratixiv_hssi_atoms.v " (procedure "proc_sim_verilog" line 7) invoked from within "proc_sim_verilog altera_pcie_bfm" Info: pcie_hard_ip_0_pcie_bfm_0: "hip_s4gx_gen1x8_qsys_tb" instantiated altera_pcie_bfm_qsys "pcie_hard_ip_0_pcie_bfm_0" Resolution 1) Include the Stratix IV GX device family when you install the Quartus II Subcription Edition. 2) Place the following files into your Quartus II Web Edition installation directory (<installation directory>/quartus/eda/sim_lib/). stratixiv_atoms (.v file) stratixiv_hssi_atoms (.v file) stratixiv_pcie_hip_atoms (.v file) stratixiv_atoms (.vhd file) stratixiv_components (.vhd file) stratixiv__hssi_atoms (.vhd file) stratixiv_hssi_components (.vhd file) stratixiv_pcie_hip_atoms (.vhd file) stratixiv_pcie_hip_components (.vhd file) Related Articles Are there any known issues when installing the Quartus II software without all the device families?How do I use the CHANGE_EDREG instruction to simulate a CRC error in Stratix, Stratix II, Arria GX, and Cyclone II and later series devices?
Description You can download the contents required to create a crc.jam file and follow the instructions below to issue the CHANGE_EDREG instruction to simulate a CRC error in Stratix®, Stratix II, Arria® GX, and Cyclone® II and later-series devices. Using the attached JAM file, modify line #9 to an arbitrary number. This is to change the CRC checksum value. DRSCAN 32, ; This will overwrite the CRC checksum in the Storage Register through the CHANGE_EDREG instruction. The CRC_Error pin will then go high, signaling a CRC error. You can use the command-line JAM player in the Quartus® II design software to execute the crc.jam file The command would be : quartus_jli -aconfig_io -cn crc.jam where n after the -c = the cable index. To find out the cable index for the USB-Blaster™, execute : quartus_jli -n Related Articles How do I use the EDERROR_INJECT JTAG instruction to simulate a CRC error in a Stratix III, Stratix IV or Arria II GX device? How do I clear the CRC error after using the CHANGE_EDREG JTAG instruction to force a CRC error?Are there any problems with channel 3 of a transceiver block after dynamic reconfiguration in Cyclone IV GX devices using Quartus II Software Version 10.1SP1 and earlier?
Description Yes due to a bug in Quartus II Software Versions 10.1SP1 and earlier, channel 3 of a transceiver block may fail to function correctly after dynamic reconfiguration in Cyclone IV GX devices. The failure symptoms are rx_freqlocked may be stuck in a deasserted (low) state when using the CDR in Automatic lock mode Receiver data errors and Rate Match FIFO overflow or underflow may be observed when using the CDR in manual lock mode Receiver data errors and an incorrect rx_clkout frequency may be observed when using the CDR in manual lock mode Transceiver-FPGA fabric interface output clocks may not toggle Affected transceiver configurations in Quartus II Software Version 10.1SP1 and earlier are detailed below. Configuration 1 detailed below may exhibit failure symptoms 1, 2, or 3 Channel Reconfiguration mode is used AND Channel 3 and channel 0 in the same transceiver block are instantiated in a single ALTGX instance AND The bottom PLL is clocking the single ALTGX instance and top PLL is clocking other circuitry Configuration 2 detailed below may exhibit failure symptom 4 Channel Reconfiguration mode is used AND Channel 3 and any other channel in the same transceiver block are instantiated in a single ALTGX instance AND Top PLL is clocking the single ALTGX instance To fix this issue install the appropriate patch, regenerate the altgx_reconfig MegaWizard, and fully recompile the design. Patch 0.36 for Quartus II Software version 10.1 PC patch 0.36 for Quartus II Software version 10.1 Linux patch 0.36 for Quartus II Software version 10.1 Readme file for patch 0.36 for Quartus II Software version 10.1 Patch 1.03 for Quartus II software version 10.1SP1 PC patch 1.03 for Quartus II Software version 10.1SP1 Linux patch 1.03 for Quartus II Software version 10.1SP1 Readme file for patch 1.03 for Quartus II Software version 10.1SP1 This issue will be fixed in a future version of the Quartus II software. Related Articles Why does rx_freqlocked signal get stuck low, even though the tx_clkout and rx_clkout are successfully reconfigured, after Channel Reconfiguration in Cyclone IV GX devices?Internal Error: Sub-system: ASM, File: /quartus/comp/asm/asm_split_bits_utility.cpp, Line: 621 Bad mask!
Description Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error when compiling a Cyclone® IV or Cyclone V design using the Functional Safety Separation Flow. During partition import of strictly preserved safety partitions, routes to top-level safe IO buffers are not correctly preserved. When the Assembler detects the preservation mismatch during the Design Modification Flow it fails with this internal error. Resolution To work around this problem, for the Quartus II software version 13.1 Update 4, download and install patches 4.30 and 4.55 from the links below. You must install the Quartus II software version 13.1 Update 4 before installing these patches. Download the Quartus II software version 13.1 Update 4 patch 4.30 for Windows (.exe) Download the Quartus II software version 13.1 Update 4 patch 4.30 for Linux (.run) Download the Readme for the Quartus II software version 13.1 Update 4 patch 4.30 (.txt) Download the Quartus II software version 13.1 Update 4 patch 4.55 for Windows (.exe) Download the Quartus II software version 13.1 Update 4 patch 4.55 for Linux (.run) Download the Readme for the Quartus II software version 13.1 Update 4 patch 4.55 (.txt) For the Quartus II software version 14.1 Update 1, download and install patch 1.04 from the links below. You must install the Quartus II software version 14.1 Update 1 before installing this patch. Download the Quartus II software version 14.1 Update 1 patch 1.04 for Windows (.exe) Download the Quartus II software version 14.1 Update 1 patch 1.04 for Linux (.run) Download the Readme for the Quartus II software version 14.1 Update 1 patch 1.04 (.txt) This problem is fixed beginning with version 15.0 of the Quartus II software.
