Error: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 or earlier, you may see this error message when generating Altera® IP on the Windows* 11 OS (Operating System). Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software.
Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Why are tREFI values in simulation and board measurement different from what is set in Altmemphy and UniPHY-based DDR2 SDRAM memory controller?
Description tREFI result in simulation and on the board might be larger than expected if you set tREFI to less than 7.8us in DDR/DDR2/LPDDR2 MegaWizard. DDR/DDR2/LPDDR2 SDRAM IP has a MEM_TREFI parameter, which defines the tREFI parameter in terms of memory clock cycles. Since the minimum value of this parameter is limited to 780, tREFI becomes larger when the memory clock is slower. For example, tREFI for DDR2 SDRAM should be 3.9us at >85C. But if the DDR2 memory clock is 125MHz(8ns), the minimum tREFI value can be 8ns x 780 = 6.24us. tREFI for DDR should be 7.8us. But if the DDR memory clock is 76.9MHz (13ns), the minimum tREFI value can be 13ns x 780 = 10.14us. Resolution As a workaround, if the DDR memory clock is below 100MHz or if you set tREFI to <7.8us on DDR2 memory, you can change the MEM_TREFI parameter in *ddrx_controller_wrapper (Altmemphy-based IP) file or *_c0 (UniPHY-based IP) file to correct the tREFI value. This problem has been fixed in Quartus® II Software Version 12.0.Error : FLEXlm version of vendor daemon is too old
Description In the Questa* FPGA Edition simulator and Questa* FPGA Starter Edition simulator version 2024.1, you might see this error or the following error if you are using the MGCLD daemon v11.16.4 “Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly” Resolution To avoid this error, upgrade to the Siemens* Flexlm (SALTD) daemon v11.19.5 Download the daemon from the download page There is a change to the Siemens* License in v11.19.5.0. If you’re running a floating license server for Siemens* licenses, manually change the VENDOR daemon line in the license file from mgcld to saltd, for example: VENDOR saltd <path to saltd> Note: Do not change any of the INCREMENT lines. Leave the INCREMENT lines with the original vendor daemon name (mgcld).How to mitigate the security vulnerability in the Nios® II Command Shell utility?
Description Due to a problem in the Quartus ® Prime Standard and Lite Edition Software version 19.1 through 24.1, the Nios® II Command Shell utility included in the Quartus ® Prime Software for Windows* is vulnerable to a Current Working Directory (CWD) planting attack. The Linux* versions are not affected. Resolution To work around this problem, replace the “Nios II Command Shell.bat” Windows Batch File located in the <drive>:\<edition>\<version number>\nios2eds\, with the attached file below. This problem is fixed beginning with the Quartus® Prime Standard and Lite Edition Software version 25.1.Why does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 LiteWhy do I get a fatal error when creating an ALTPLL IP?
Description Due to a problem in the Quartus® Standard Edition Software version 23.1, you might see a fatal error when creating an ALTPLL IP Using the MegaWizard Plug-In Manager. Resolution To work around this problem, download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1 Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Windows (.exe) Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Linux (.run) Readme for Quartus® Prime Standard Edition Software v23.1 Patch 0.02std (.txt) This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IPWhy does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Cyclone® IV Device Handbook: Known Issues
Description Issue 236435: Volume 1, Chapter 11, Power Requirements for Cyclone IV Devices, Version 1.3 In Table 11.1, note 3 states that “Device package F484 of EP4CGX30 have four VCC_CLKIN dedicated clock input I/O bank located at banks 3A, 3B, 8A, and 8B”. This is not correct. The EP4CGX30F484 does not have I/O bank 8B, so it only has three VCC_CLKIN dedicated clock inputs which hare located in banks 3A, 3B, and 8A. Issue 218194: Volume 3, Chapter 1, Cyclone IV Device Datasheet, Version 1.8 Note 2 states that the 10uA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be observed when the diode is on. It should state that the 10uA I/O leakage current limit is applicable when the internal clamping diode is either enabled or disabled, and is reverse biased. A higher current can be observed when the diode is forward biased. Issue 137998: Volume 3, Chapter 1, Cyclone IV Device Datasheet, Version 1.7 Table 1-25 shows the PLL specifications for Cyclone IV devices. Note 1 indicates the specifications apply to both general purpose PLLs (GPLL) and multipurpose PLLs (MPLL). This table is incomplete. MPLLs support a VCO operating range from 600 to 1600MHz in the following Cyclone IV GX devices: EP4CGX30*, EP4CGX50, EP4CGX110, EP4CGX150. * Applies to the F23 package only. Issue 131091: Cyclone® IV Devices Datasheet, Version 1.7 Note 5 for Table 1-3: Recommended Operating Conditions for Cyclone IV E Devices instructs you to select C8 as the target device when designing for an I7 device in the Quartus® II software. This instruction is incorrect. In the Quartus® II software, targeting a C8 device is not necessary because there is option to set 125 °C as the maximum temperature in the Junction temperature range on the Temperature page of the Settings dialog box. Issue 119744: Volume 1, Chapter 8, Configuration and Remote System Upgrades in Cyclone IV Devices, Version 1.6 In Table 8-17 and 8-18 it shows that DATA[0] as a dedicated pin "Yes" but should be a "-" as the DATA0 pin will be available as a user I/O pin after configuration in Active Serial (AS) mode but not in Passive Serial (PS) or Fast Passive Parallel (FPP) modes. Table 8-19 will also be updated to reflect this. Issue 119386: Volume 1, Chapter 11, Power Requirements for Cyclone IV Devices, Version 1.2 Table 11-1 says in note 4 VCC_CLKIN for I/O banks 3A and 8A only supports 2.5V. This is not correct, when not used for HSSI refclk, the clock input pins in banks 3A and 8A support 1.2 V/ 1.5 V/ 1.8 V/ 2.5 V/ 3.0 V/ 3.3V voltages. Issue 66850: Volume 1, Chapter 8, Configuration and Remote System Upgrades in Cyclone IV Devices, Version 1.4 Notes to Table 1 of Table 8-17 and Note 4 of Table 8-18 state that "The CRC_ERROR pin is a dedicated output by default. Optionally, you can enable the CRC_ERROR pin as an open-drain output in the CRC Error Detection tab of the Device and Pin Options dialog box" which is incorrect. The Notes to Table will be updated to state "Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled in the Quartus II software from the Error Detection CRC tab of the Device and Pin Options dialog box. When using this pin, connect it to an external 10K-ohm pull-up resistor to an acceptable voltage that satisfies the input voltage of the receiving device." Issue 35742: Volume-2, Chapter 1, Cyclone IV Transceivers Architecture, Version 3.3 In the Transceiver Clocking Architecture section, note (1) under Figure 1-27 states, "VICM can be sourced from the 2.5-V supply with a voltage divider circuit (typically two 1-kohm resistors)." That would make the VICM to be 1.25V. However, in the Cyclone IV Device Datasheet, the specification of VICM (AC coupled) for the reference clock input is 1.1V -5, which is correct information. Figure 1-27 will be updated in a future version of the handbook. Issue 46239: Volume 3, Chapter 1, Cyclone IV Device Datasheet, Version 1.5 The pin capacitance in Table 1-11 in the Cyclone IV Datasheet applies to FBGA, UBGA, and MBGA packages. Issue 379673: Volume 1, Chapter 8, Configuration and Remote System Upgrades in Cyclone IV Devices, Version 1.3 The correct frequency for CLKUSR in Cyclone IV devices is 40MHz during user mode. In the Cyclone IV handbook there is a section called "Overriding Internal Oscillator" which states that CLKUSR is 80MHz, this is incorrect and will be fixed in a future version of this handbook. Issue 368288: Volume 1, Chapter 9, SEU Mitigation in Cyclone IV Devices, Version 1.1 Table 9-2 incorrectly states the CRC_ERROR pin is a dedicated output with optional open-drain functionality. The CRC_ERROR pin, when used for the error detection circuitry, only functions as open-drain, it cannot drive high logic levels, and must have an external 10-KΩ pull-up resistor to an acceptable voltage to meet the receiving device requirements. Issue 363311: Volume 3, Chapter 1, Cyclone IV Device Datasheet, Version 1.5 The Vicm specifications for the REFCLK pins are missing in table 1-21. They are as follows: Vicm (AC coupled) = 1.1V /-5% Vicm (DC Coupled), Min = 250mV and Max = 550mV Resolution Resolved Issues: Issue 10005660: Volume 1, Chapter 1, Cyclone IV Device Family Overview, Version 1.1 Figure 1-3 was updated with correct package ordering codes for the F256 and E144 packages for Cyclone IV E devices in version 1.2. Issue 10005688: Volume 1, Chapter 1, Cyclone IV Device Family Overview, Version 1.1 Note (2) for Table 1-6 was updated with the correct core voltage requirement for Cyclone IV E devices in version 1.2. Issue 10006437: Volume 2, Chapter 3, Cyclone IV Dynamic Reconfiguration, Version 1.0 Updated bit descriptions for rx_dataoutfull[31..0]. Issue 10006413: Volume 1, Chapter 8, Configuration and Remote System Upgrades in Cyclone IV Devices, Version 1.2 Clarification added for tCF2ST1(nCONFIG high to nSTATUS high) timing. Issue 10006558: Volume 2, Chapter 3, Cyclone IV Dynamic Reconfiguration, Version 1.0 DC Gain (rx_eqdcgain) settings updated in table 3-2. Issue 359178: Volume 2, Chapter 1, Cyclone IV Transceiver Architecture, Version 1.0 GXB block labels updated in the PLL Input Reference Clocks in Transceiver Operation for F484 and Larger Packages figure. Issue 364247: Volume 1, Chapter 10, JTAG Boundary-Scan Testing for Cyclone IV Devices, Version 1.1 When running boundary scan using a pre-configuration BSDL file prior to device configuration you must hold the nCONFIG pin low. Issue 363791: Volume 1, Chapter 10, JTAG Boundary-Scan Testing for Cyclone IV Devices, Version 1.1 IDCODE values updated for EP4CGX50 and EP4CGX30 devices in the F23 package. Issue 377866: Volume 1, Chapter 8, Configuration and Remote System Upgrades in Cyclone IV Devices, Version 1.3. Guidelines added to avoid timing violations for Cyclone IV E devices with 1.0V core voltage in multi-device AS configuration where the slave device is configured by PS mode. Issue 35734: Volume 1, Chapter 6, I/O Features in the Cyclone IV Devices, Version 2.3 Page 4 describes the programmable slew rate control option and states "You cannot use the programmable slew rate feature when using OCT with calibration." Programmable slew rate is available when using OCT without calibration. There is no documentation error. Related Articles Why do I get a different IDCODE for EP4CGX50 and EP4CGX30 devices in the F23 package? What is the typical value for the 40 MHz DCLK in Cyclone IV devices?
