18 Results
Why might the Low Latency 40G and 100Gbps Ethernet MAC pause quanta time be shorter than expected?
...mplemented in the Low Latency 40G and 100Gbps Ethernet MAC and PHY Megacore® Function flow control implementation. Therefore, if the TX is not idle when the pause quanta are loaded, the requested pause time m...69Views0likes0CommentsWhy do I see hold time violations in the Low Latency 40G Ethernet Intel® FPGA IP core when KR4 is enabled?
Description Due to a problem with the Low Latency 40G Ethernet Intel® FPGA IP core on Intel® Stratix® 10 FPGA, you might see minor hold time violations when the KR4 feature is enabled. R...66Views0likes0CommentsWhy am I writing and reading back incorrect values when accessing the transceiver PMA and PCS registers within the Intel® Stratix® 10 Low Latency 40G Ethernet design example?
Description Due to a problem in the Intel® Quartus® Prime Software version 18.1, writes to the transceiver PMA and PCS registers within the Intel® Stratix® 10 Low Latency 40G Ethernet d...53Views0likes0CommentsWhy are the o_clk_rec_div and o_clk_rec_div64 ports improperly constrained when examining the timing reports of the F-tile Ethernet Intel® FPGA Hard IP?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, the .sdc files generated for the F-tile Ethernet Intel® FPGA Hard IP improperly constrain the o...113Views0likes0CommentsWhy does the runt statistics register of Legacy 40/100G Ethernet IP core read back as "X" in simulation?
Description Due to a change in runt handling behavior in the Intel® Quartus® Prime Software v16.1, the runt statistics register might read back as "X" in simulation in the Legacy 40/100G Ethernet M...100Views0likes0CommentsWhy are the o_clk_rec_div and o_clk_rec_div64 ports improperly constrained when examining the timing reports of the F-Tile Ethernet Multirate Intel® FPGA IP?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, the .sdc files generated for the F-tile Ethernet Multirate Intel® FPGA IP improperly constrain t...84Views0likes0CommentsHow do I set the paramter FAST_SIMULATION of my 40- and 100-Gbps Ethernet MAC and PHY in VHDL?
Description In Quartus® II software version v13.0SP1 and earlier you must manually modify the IP libraries of the 40- and 100-Gbps Ethernet MAC and PHY IP Core to set the parameter FAST_SIMULATION i...61Views0likes0CommentsWhy does the Intel® Stratix® 10 Low Latency 40-Gbps Ethernet IP Core fail to detect and flag oversized packets when the frame length is greater than or equal to 0x10000?
Description Due to a code limitation, the frame length counter in the Intel® Stratix® 10 Low Latency 40-Gbps Ethernet IP Core will overflow when the frame length is greater than or e...64Views0likes0Comments