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Why does the Quartus® Prime Pro Edition Software report that no IOPLL is available when placing the Low Latency E-Tile 40G Ethernet FPGA IP in an HPS shared GPIO Bank?
Description Due to a clocking limitation of HPS Shared GPIO Bank, the Low Latency E-Tile 40G Ethernet FPGA IP cannot be placed in an HPS Shared GPIO Bank when a design targets Agilex® 7 FPGA F-S...76Views0likes0CommentsWhy might the Low Latency 40G and 100Gbps Ethernet MAC pause quanta time be shorter than expected?
...mplemented in the Low Latency 40G and 100Gbps Ethernet MAC and PHY Megacore® Function flow control implementation. Therefore, if the TX is not idle when the pause quanta are loaded, the requested pause time m...Why am I writing and reading back incorrect values when accessing the transceiver PMA and PCS registers within the Intel® Stratix® 10 Low Latency 40G Ethernet design example?
Description Due to a problem in the Intel® Quartus® Prime Software version 18.1, writes to the transceiver PMA and PCS registers within the Intel® Stratix® 10 Low Latency 40G Ethernet d...Why are the o_clk_rec_div and o_clk_rec_div64 ports improperly constrained when examining the timing reports of the F-tile Ethernet Intel® FPGA Hard IP?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, the .sdc files generated for the F-tile Ethernet Intel® FPGA Hard IP improperly constrain the o...204Views0likes0CommentsWhy does the runt statistics register of Legacy 40/100G Ethernet IP core read back as "X" in simulation?
Description Due to a change in runt handling behavior in the Intel® Quartus® Prime Software v16.1, the runt statistics register might read back as "X" in simulation in the Legacy 40/100G Ethernet M...198Views0likes0CommentsWhy are the o_clk_rec_div and o_clk_rec_div64 ports improperly constrained when examining the timing reports of the F-Tile Ethernet Multirate Intel® FPGA IP?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, the .sdc files generated for the F-tile Ethernet Multirate Intel® FPGA IP improperly constrain t...185Views0likes0Comments