Why is there a mismatch in the FFT Intel® FPGA IP output result in simulation between the IP-generated MATLAB* model and the HDL model?

Description

Due to a problem with the FFT Intel® FPGA IP version 19.1, you may observe the above problem in the simulation if the Data Output Width of the IP is not configured to the maximum supported width.

Resolution

To work around this problem configure the Data Output Width to the maximum supported width in IP.

This problem is currently not scheduled to be fixed in a future version of the FFT Intel® FPGA IP.

Updated 2 months ago

Version 3.0

arria® 10 fpgas and socs

arria® ii fpgas

arria® v fpgas and socs

cyclone® iv fpgas

cyclone® v fpgas and socs

fpga dev tools quartus® prime software pro

fpga dev tools quartus® prime software standard

max® 10 fpgas

Stratix® 10 FPGAs and SoCs

stratix® iv fpgas

Knowledge Base Article

Why is there a mismatch in the FFT Intel® FPGA IP output result in simulation between the IP-generated MATLAB* model and the HDL model?

Description

Resolution