Knowledge Base Article

Why does Triple-Speed Ethernet Intel® FPGA IP fail for 10M/100M speeds when MAC is configured for 8-bit FIFO?

Description

Due to problem in the transmitter of the Triple-Speed Ethernet Intel® FPGA IP and the F-Tile Triple-Speed Ethernet Intel® FPGA IP, the design fails when the MAC only variant is configured for an 8-bit FIFO.

Resolution

This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 23.1.

Updated 3 months ago
Version 2.0
agilex™ 7 fpgas and socs
arria® 10 fpgas and socs
arria® ii fpgas
arria® v fpgas and socs
cyclone® iv fpgas
cyclone® v fpgas and socs
fpga dev tools quartus® prime software pro
max® 10 fpgas
stratix® 10 fpgas and socs
stratix® iv fpgas
No CommentsBe the first to comment