Knowledge Base Article

Why does the DisplayPort Intel® FPGA IP fail to output video when Vtotal of Main Stream Attribute (MSA) field is greater than 13-bit width?

Description

Due to a problem in version 14.0 and later of the Intel® Quartus® Prime software, the DisplayPort Intel® FPGA IP Pixel Clock Recovery Interface Hsync and Vsync signals stick low when the condition below is met:

  • Video resolution with Vtotal Main Stream Attribute (MSA) field exceeding 13-bit width or 8191 in decimal.
Resolution

This problem is fixed starting from the Intel® Quartus® Prime Pro Edition version 20.1 Software onwards.

Updated 26 days ago
Version 2.0
Arria® 10 FPGAs and SoCs
Arria® V FPGAs and SoCs
critical
Cyclone® 10 GX FPGA
Cyclone® V FPGAs and SoCs
fpga dev tools quartus® prime software pro
FPGA Dev Tools Quartus® Prime Software Standard
Stratix® 10 FPGAs and SoCs
Stratix® V FPGAs
troubleshooting
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