Error (18212): Cannot load final snapshot for partition "root_partition”
Description Due to a problem in Intel® FPGA SDK for OpenCL™ version 19.1, you may see an OpenCL™ kernel compile crash after installing the Intel® Quartus® Prime Software 19.1 0.03 patch. The Intel® FPGA SDK for OpenCL™ uses BAK-cache (a local copy in a temporary folder of the local machine) to speed up subsequent kernel compiles. The error messages are shown below. It should be visible on the standard output and printed in quartus_sh_compile.log. Error (18212): Cannot load final snapshot for partition "root_partition" - the partition is not in a version compatible format. Error: Quartus Prime MIF/HEX Update was unsuccessful. 1 error, 0 warnings Error (23035): Tcl error: Error (23031): Evaluation of Tcl script scripts/post_flow_pr.tcl unsuccessful Resolution There are two ways to work around this problem Approach 1 (Recommended) Delete your local BAK cache. The problem will be solved for the next and all compiles onwards. For Windows, remove $ENV{'USERPROFILE'}\\AppData\\Local\\aocl For Linux, remove /var/tmp/aocl/$ENV{USERNAME} Approach 2 Run “aoc” argument with this option “-no-read-bsp-bak-cache”. Note this will slow down compile by an hour aoc -no-read-bsp-bak-cache <kernel> This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.3.Ubuntu Operating System Support Requires Intel® FPGA Software Version 17.0 Update 1
Description The following publications incorrectly state that Intel® Quartus® Prime Version 17.0 and Intel FPGA SDK for OpenCL™ Version 17.0 provide support for Ubuntu operating systems: Intel Quartus Prime Pro Edition Software and Device Support Release Notes Version 17.0 (RN-01082-17.0.0 published 2017.05.08) Intel Quartus Prime Standard Edition Software and Device Support Release Notes Version 17.0 (RN-01080-17.0 published 2017.05.08) Intel FPGA SDK for OpenCL Version 17.0 Release Notes (RN-OCL004 published 2017.05.08) Ubuntu operating system support requires Version 17.0 Update 1.Installing an unsigned driver might cause an error in the Altera SDK for OpenCL running on Windows 8.1
Description If you run the Altera SDK for OpenCL version 15.1 on Windows 8.1 and you install an unsigned driver, you might encounter the following error messages: difx_install_preinstall_inf: err e000024b, last event 0, last error 0. UNKNOWN difx_install_preinstall_inf: err e000022f, last event 0, last error 0. UNKNOWN Resolution Prior to installing an unsigned driver, disable driver signature enforcement by performing the following steps: On the Windows login screen or under the Charms bar, open the power options menu. Hold the Shift key while you click Restart from the power options menu. After your computer reboots, select the Troubleshoot option. Select Advanced Options. Select Startup Settings. When prompted, click Restart to reboot your computer. When the Startup Settings menu appears, press the F7 key to choose the Disable driver signature enforcement option. After your computer restarts, you can install unsigned drivers.SCDC Values in HDMI Parameter Editor Not Passed Into the HDMI IP Core
Description The values specified for the Manufacturer OUI, Device ID String, and Hardware Revision parameters for the Altera HDMI sink core are not passed into the HDMI sink core properly. As a result, the SCDC registers are not configured properly for these input values. This issue affects all supported devices. Resolution There is no workaround for this issue. This issue is fixed in version 16.0 of the HDMI IP core.Creating OTN_cascade or SDI_cascade Instances at a Low or Medium IP Bandwith Causes the Arria® 10 and Cyclone® 10 GX fPLL or ATX PLL IP Parameter Editor GUI to Encounter an Error Related to f_max_pfd
Description If you set the fPLL or ATX PLL IP bandwidth to low or medium for Arria® 10 and Cyclone® 10 GX devices while attempting to create OTN_cascade or SDI_cascade instances, the IP Parameter GUI might display an error that relates to f_max_pfd. This issue affects the Quartus® Prime Standard Edition Software and the Quartus® Prime Pro Edition Software. Resolution In the fPLL or ATX PLL IP Parameter Editor, you cannot select the bandwidth after you select the OTN or SDI protocol. Therefore, before you create OTN_cascade or SDI_cascade instances, first select Basic from the Protocol mode pull-down menu and then select High from the Bandwith pull-down menu.Why does the Low Latency 100G Ethernet Intel® FPGA IP fail timing on Intel® Stratix® 10 FPGA?
Description When using the Low Latency 100G Ethernet Intel® FPGA IP with RSFEC and/or KR mode enabled on Intel® Stratix® 10 FPGA, timing violations can be observed. Resolution To work around these timing violations when using Intel® Quartus® Prime version 18.0 or 18.1: a. Check the Low Latency 100G Ethernet Intel® FPGA IP placement using the Quartus Prime Chip Planner. If any hard block in the core is in the way of the placement of the Intel® Stratix® 10 100G IP placement, it may create long routing and result in bad timing. If this is the case, please choose a different set of transceiver locations when possible. b. Try seed sweeping to get a better timing result. This problem has been improved but not fixed in version 19.1 of the Intel® Quartus® Prime Edition Software.Performance Risk Running Triple Speed Ethernet LVDS in Arria 10 Devices
Description There may be a performance risk if you use the Triple Speed Ethernet IP variant with LVDS I/O for PMA implementation in Arria 10 devices for Quartus Prime versions 17.0.2 and earlier. Resolution To avoid the performance risk, Intel® recommends that you regenerate the Triple Speed Ethernet IP core and recompile the design in the Intel Quartus® Prime software version 17.1 or later. Refer to the latest Triple Speed Ethernet User Guide version 17.1 for more information. The following patch provides a solution to the Triple Speed Ethernet IP variant with LVDS I/O for PMA implementation in Intel Arria 10 devices for Intel Quartus Prime version 17.0.2. Download and install the appropriate patch from the following links: Quartus Prime Pro Edition software version 17.0.2 patch 2.05 for Window Quartus Prime Pro Edition software version 17.0.2 patch 2.05 for Linux Quartus Prime Pro Edition software version 17.0.2 ReadMe for patch 2.05 Quartus Prime Standard Edition software version 17.0.2 patch 2.05std for Window Quartus Prime Standard Edition software version 17.0.2 patch 2.05std for Linux Quartus Prime Standard Edition software version 17.0.2 ReadMe for patch 2.05stdWhy does the Intel® Arria® 10 and the Intel® Cyclone® 10 Avalon®-ST or Avalon® -MM Interface for PCI Express* IP example design report ignored SDC constraint warnings?
Description When compiling the Intel® Arria® 10 or the Intel® Cyclone® 10 Avalon®-ST or Avalon® -MM Interface for PCI Express* IP example design generated using Intel® Quartus® Prime Software version 19.4 or earlier, the following ignored SDC constraint warnings will be seen. Warning(332174): Ignored filter at altera_xcvr_native_a10_false_paths.sdc(63): *twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n could not be matched with a pin Warning(332174): Ignored filter at altera_xcvr_native_a10_false_paths.sdc(53): *twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n could not be matched with a pin Warning(332049): Ignored set_max_skew at altera_pci_express.sdc(34): Argument -to with value [get_registers {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|dbg_rx_data_reg[*] *|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|dbg_rx_datak_reg[*]}] contains zero elements Warning(332049): Ignored set_max_skew at altera_pci_express.sdc(35): Argument -to with value [get_registers {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|dbg_rx_data_reg_1[*] *|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|dbg_rx_datak_reg_1[*]}] contains zero elements Warning(332049): Ignored set_max_delay at altera_pci_express.sdc(37): Argument is an empty collection Warning(332174): Ignored filter at altera_pci_express.sdc(38): *|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_sc_bitsync_node:rx_polinv_dbg.dbg_rx_valid_altpcie_sc_bitsync_1|altpcie_sc_bitsync:altpcie_sc_bitsync|altpcie_sc_bitsync_meta_dff[0] could not be matched with a clock or keeper or register or port or pin or cell or partition Warning(332049): Ignored set_false_path at altera_pci_express.sdc(38): Argument is not an object ID Warning(332174): Ignored filter at altera_pci_express.sdc(39): *|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_sc_bitsync_node:rx_polinv_dbg.dbg_rx_valid_altpcie_sc_bitsync|altpcie_sc_bitsync:altpcie_sc_bitsync|altpcie_sc_bitsync_meta_dff[0] could not be matched with a clock or keeper or register or port or pin or cell or partition Warning(332049): Ignored set_false_path at altera_pci_express.sdc(39): Argument is not an object ID These SDC constraint warnings can be ignored. Resolution User can safely ignore these SDC constraint warningsWhy does the Intel® PCIe* Hard IP run into recursive replay timer timeout, replay num rollover and link recovery when sending traffic?
Description You might see timeout, rollover, and recovery because of Start of Packet(SOP) pointer buffer overflow. The SOP pointer buffer can overflow during replay because of internal error message or TLPs submitted from user side for transmission when the following trigger conditions are met: - ACK packets are lost or not received by Intel® PCIe* Hard IP under a high bit error rate link conditions - Link partner is unable to ACK packets at regular intervals as per the spec for unknown reasons If the above trigger conditions persists, then there are chances that internal SOP pointer buffer will reach the full condition. Every replay after this will cause overflow because of error message scheduling (Replay Timeout, Replay Num Rollover) or TLPs are submitted from user side for transmission. Resolution There is no workaround to this problem. This problem will not be fixed in a future release of the Intel® Quartus® Prime software.Timing Violation for Arria 10 DisplayPort Design
Description When you run the DisplayPort design for Arria 10 devices, the design may encounter timing violation on the rx_restart signal. This signal is clocked as rx_std_clkout in the DisplayPort IP core, but connects to the reset pin in the reset controller running on the Avalon Memory-Mapped (Avalon-MM) clock domain. Resolution To work around this issue, add a reset synchronizer for the rx_restart signal at the top level before you connect to the reset controller. This issue is fixed in version 15.1 Update 1 of the DisplayPort IP core.