Why does the MIPI link fail despite successful FPGA reconfiguration (Phase 2) in HPS First boot mode on Agilex® 5 or Agilex® 3 SoC FPGAs?
Description For HPS First Agilex® 5 or Agilex® 3 SoC FPGAs designs that include shared IO in the HPS EMIF banks, a firmware problem may cause the MIPI link to fail. This is due to the shared IO potentially getting stuck in reset after FPGA reconfiguration (Phase 2). This failure is not observed for FPGA First designs or designs that do not use shared IO. Refer to 3.5. Agilex® 5 EMIF IP for Hard Processor Subsystem (HPS) or A.1.13.1. Restrictions on I/O Bank Usage for Agilex® 3 EMIF IP with HPS for more information regarding IO sharing. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.Why does the Stratix® 10 Interlaken (2nd Generation) IP Example Design fail in non-continuous mode (Transfer Mode selection set to packet)?
Description Due to a problem with the Stratix® 10 Interlaken (2nd Generation) IP Example Design Packet Transfer mode pattern generator may generate incorrect payload data if the signal itx_ready deasserts during the last packet transfer (i.e. packet 100). Resolution To work around this problem using Intel® Quartus® Prime v19.1 modify the files "ilk_pkt_gen.sv" and "ilk_pkt_gen_mseg.sv" found in the folder /<your example design>/example_design_s10/rtl/as shown below. ilk_pkt_gen.sv Change From: always @(posedge clk) begin if (tx_usr_srst_r[0]) begin stop_pkt <= 1'b0; end else if (pkt_cnt == 7'd100 && !continuous_pkt ) begin // end else if (pkt_cnt[6] & pkt_cnt[5] & pkt_cnt[2]) begin stop_pkt <= 1'b1; end end Change To: always @(posedge clk) begin if (tx_usr_srst_r[0]) begin stop_pkt <= 1'b0; end else if (pkt_cnt == 7'd100 && !continuous_pkt && tx_eopbits_nxt[3]) begin // end else if (pkt_cnt[6] & pkt_cnt[5] & pkt_cnt[2]) begin stop_pkt <= 1'b1; end end ilk_pkt_gen_mseg.sv Change From: always @(posedge clk) begin if (tx_usr_srst_r[0]) begin stop_pkt <= 1'b0; end else if (pkt_cnt_sop == 7'd100 && !continuous_pkt ) begin // end else if (pt_cnt[6] & pkt_cnt[5] & pkt_cnt[2]) begin stop_pkt <= 1'b1; end end Change To: always @(posedge clk) begin if (tx_usr_srst_r[0]) begin stop_pkt <= 1'b0; end else if (pkt_cnt_sop == 7'd100 && !continuous_pkt && (state == ST_C3) && tx_ready) begin // end else if (pkt_cnt[6] & pkt_cnt[5] & pkt_cnt[2]) begin stop_pkt <= 1'b1; end end The problem has been fixed starting with Quartus® Prime Pro Edition software version 19.2.Why does the Synopsys VCS* simulator produce incorrect simulation results for Agilex® 5 FPGAs?
Description The Agilex™ 5 FPGAs do not support the Synopsys VCS* two-step flow (compile and elaborate in one step and simulate in the next). You might see incorrect simulation results when simulating a multi-IP design with Synopsys VCS* simulator if you specify all IP and Quartus® simulation library source files using a single VCS command line, run_vcs. Resolution Follow these steps to use Synopsys VCS* simulator with VCS MX flow: Create design libraries using the mkdir command Compile all IP and Quartus® simulation library source files into their respective libraries using vlogan or vhdlan commands Elaborate the top-level design using the vcs command without specifying the source files compiled in Step 2 Simulate your design using the generated simv executable file The above steps are sometimes called VCS or VCS MX three-step flow (compile in one step, elaborate in the next step, and simulate in the final step). For information on which library files to be compiled, command examples, and command arguments, refer to the Platform Designer-generated VCS MX simulation setup script (/synopsis/vcsmx/vcsmx_setup. sh). If you were previously using the Platform Designer-generated VCS simulation setup script (/synopsys/vcs/vcs_setup.sh), switch to using the Platform Designer-generated VCS MX simulation setup script (/synopsys/vcsmx/vcsmx_setup.sh). Refer to Quartus® Prime Pro Edition User Guide: Third-party Simulation for more guidelines on incorporating the generated Synopsys VCS MX simulation scripts into a top-level project simulation setup script. Agilex® 5 FPGA no longer supports the VCS 2-step flow; only the VCS 3-step flow is supported.What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.3.1?
Description The latest device firmware for the Quartus® Prime Pro Edition Software version 24.3.1 can be downloaded from the following links. Fixes for the following problems are included in the latest release (The newest release contains all prior fixes and supersedes earlier device firmware releases). Change Log Firmware version 1.01fw: This patch fixes an issue on Agilex® 7 FPGA devices where the HPS may become stuck at the First Stage Bootloader (FSBL). Firmware version 1.06fw: This patch includes EMIF and HBM2e firmware updates for Agilex® 7 M-Series ES and production devices. Firmware version 1.15fw: This patch fixes an issue where SDM hangs when reconfiguring back-to-back. Please also see the following links: Updating the SDM Firmware in the Agilex® 7 FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution Download the latest device firmware below. Note: Patches must be applied to the Quartus® Prime Pro Edition Software and the Quartus® Prime Pro Edition Software Programmer and Tools. Recompilation is not required. All programming files should be recreated. Re-run the programming file generation or conversion using the Quartus® Prime Software programming file generator.Why does the Stratix® 10 EMIF Toolkit report DQS Enable Calibration failure?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 19.3 and earlier, the Intel Stratix® EMIF Toolkit calibration report may show a DQS Enable Calibration failure even though both the DQ/DQS read and write margins show passing valid window values. This DQS Enable Calibration failure report can be ignored if the DQ/DQS read and write margins show passing valid window values. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 19.3 and earlier, you can also verify that the local_cal_success signal is asserted using the Signal Tap Logic Analyzer tool. This problem is fixed in the Quartus Prime Pro Edition Software version 19.4 and later.Why do several IP design examples fail on the Agilex® 7 FPGA Series Transceiver SoC Development Kit?
Description The following IP Cores generate example designs for the Agilex® 7 FPGA Series Transceiver SoC Development Kit with incorrect VID settings. 1) Serial Lite IV IP 2) Interlaken (2nd Generation) IP 3) Triple-Speed Ethernet IP 4) E-Tile Dynamic Reconfiguration IP 5) E-Tile Hard IP for Ethernet and CPRI PHY IP 6) JESD204B IP 7) JESD204C IP 8) Ethernet Subsystem IP Resolution The correct VID settings can be found in section 6.1, Add SmartVID settings in the Quartus® Prime QSF file of the Agilex® F-Series Transceiver-SoC Development Kit User Guide. Update the design examples with the correct VID settings as shown below: set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ" set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 42 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00 set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 set_global_assignment -name USE_CONF_DONE SDM_IO16 set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13" set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why are the inputs and/or outputs from my Agilex® 7 FPGA device inverted?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and later, signals from the banks listed below may be inverted. This only affects IO Cells where any of the IO registers are enabled. Device GPIO Bank AGIB041, AGID041 3C and 3D AGFB006, AGFB008 3C and 3D AGFB012, AGFB014 3C and 3D AGFB019, AGFB023, AGFD019, AGFD023 AGIB019, AGIB023, AGID019, AGID023 3A and 3B AGFB022, AGFB027 AGIB022, AGIB027 3C and 3D Resolution To work around this problem, disable register packing for these GPIO banks. This problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1.What is the latest device firmware for the Agilex® FPGA and Stratix®10 FPGAs?
Description Altera® recommends using the latest version of the Quartus® Prime Pro Edition Software and the latest available device firmware. Please also see the following user guides: Updating the SDM Firmware in the Agilex® 7 FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution The latest device firmware available for the Quartus® Prime Pro Edition Software can be downloaded from the following links: Quartus Prime Pro Edition Software version 25.3 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 25.3? Quartus Prime Pro Edition Software version 25.1 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 25.1? Quartus Prime Pro Edition Software version 24.3.1 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.3.1? Quartus Prime Pro Edition Software version 24.3 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.3? Quartus Prime Pro Edition Software version 24.2 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.2? Quartus Prime Pro Edition Software version 24.1 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.1? Quartus Prime Pro Edition Software version 23.4 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.4? Quartus Prime Pro Edition Software version 23.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.3? Quartus Prime Pro Edition Software version 23.2 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.2? Quartus Prime Pro Edition Software version 23.1 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.1? Quartus Prime Pro Edition Software version 22.4 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.4? Quartus Prime Pro Edition Software version 22.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.3? Quartus Prime Pro Edition Software version 22.2 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.2? Quartus Prime Pro Edition Software version 22.1 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.1? Quartus Prime Pro Edition Software version 21.4 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.4? Quartus Prime Pro Edition Software version 21.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.3? Quartus Prime Pro Edition Software version 21.2 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.2? Quartus Prime Pro Edition Software version 21.1 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.1? Quartus Prime Pro Edition Software version 20.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 20.3?What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.2?
Description The latest device firmware for Quartus® Prime Pro Edition Software version 24.2 is available for download below. Fixes for the following problems are included in the latest release (The newest release contains all prior fixes and supersedes earlier device firmware releases). Change Log Firmware version 0.04fw: This patch fixes the issue of incorrect data retrieval in the GET_I2C_TELEMETRY command. Firmware version 0.10fw: This patch fixes to reissue PLL lock request to achieve true independent PERST. Firmware version 0.54fw: This patch fixes issue where the HPS will get stuck at FSBL on certain units above Quartus 22.2B94 / or with firmware above 22.4B94. Firmware version 0.59fw: This patch includes fix to improves voltage sensor reading stability. Please also see the following links: Updating the SDM Firmware in the Agilex® 7 FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution Download the latest device firmware below. Note: Patches must be applied to the Quartus® Prime Pro Edition Software and the Quartus® Prime Pro Edition Software Programmer and Tools. Recompilation is not required. All programming files should be recreated. Re-run programming file generation or conversion using the Quartus® Prime Software programming file generator.What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.3?
Description The latest device firmware for Quartus® Prime Pro Edition Software version 24.3 is available for download below. Fixes for the following problems are included in the latest release (The newest release contains all prior fixes and supersedes earlier device firmware releases). Change Log Firmware version 0.12fw: This patch fixes potential HBM2E calibration issues for Agilex® 7 FPGA M-Series devices. Firmware version 0.22fw: This patch fixes a rare scenario issue where the device hangs when reconfiguring back-to-back. The fix includes an update to the polling scheme in firmware to address the issue. Firmware version 0.25fw: This patch fixes an issue on Agilex® 7 FPGA devices where the HPS may become stuck at the First Stage Bootloader (FSBL). Firmware version 0.27fw: This patch fixes an issue where mailbox temperature inquiry would result in incorrect reading. It also fixes an issue where QSPI Write/Read would result in HW Ready error, an racing condition. Firmware version 0.34fw: This patch fixes a race condition in handling SHA isr and resumption of FPGA data blocks. Drain DMA post a configuration/PR to flush out left over data if any. Please also see the following links: Updating the SDM Firmware in the Agilex® 7 FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution Download the latest device firmware below. Note: Patches must be applied to the Quartus® Prime Pro Edition Software and the Quartus® Prime Pro Edition Software Programmer and Tools. Recompilation is not required. All programming files should be recreated. Re-run the programming file generation or conversion using the Quartus® Prime Software programming file generator.