How accurate are the CDR Function Pins in the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA Pinout Files?
Description Due to a problem in the pinout files and the Quartus® Prime Pro Edition Software version 25.1 and prior for the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA, the CDR function pin assignments in the bottom index sub-bank are incorrectly documented. Specifically: Pins with index 10/11, 22/23, 34/35, and 46/47 are mistakenly listed as supporting the CDR function. Conversely, pins with index 0/1, 12/13, 24/25, and 36/37, which do support the CDR function, are incorrectly marked as not supporting it. Resolution To work around this issue, users should update their board designs by reassigning the CDR function from the incorrect pin index to the correct ones as follows: Incorrect Pin Index Correct Pin Index 10/11 0/1 22/23 12/13 34/35 24/25 46/47 36/37 Designers are advised to validate pin assignments using the LVDS SERDES IP in Quartus® Prime Pro Edition Software rather than relying solely on the pinout files or Pin Planner. This problem is scheduled to be fixed in the pinout files and in a future release of Quartus® Prime Pro Edition Software.Why are there functional failures after partial reconfiguration in Agilex™ 7/5/3 FPGA designs?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 23.2 to 25.1, you might have functional failures after partial reconfiguration (PR) in some Agilex™ FPGA devices. The failure has FPGA unit and design dependencies and does not occur in all devices. It is a time zero failure for the affected FPGA units. The problem affects all Agilex™ FPGA portfolio devices. Resolution To work around this problem: Convert your base SOF to RBF/JIC/RPD* (Base bitstream for full-chip configuration) and PR PMSF to RBF (PR bitstream) using the Quartus® Programming File Generator v25.1.1. Use the Quartus® Programmer v25.1.1 to program the Base and PR bitstreams. The problem is fixed starting with the Quartus® Prime Pro Edition Software version 25.1.1. *RPD file format is for third party programming methods, not supported in Quartus® Prime Programmer.Does Agilex™ 3 support SmartVID optional functions for some pin names in the Quartus® Prime Pro Edition Software?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 for Agilex™ 3 FPGA devices, the Quartus® Prime Pro Edition Software incorrectly reports that SmartVID feature-related optional pin functions are available. The Agilex™ 3 FPGA devices do not support the SmartVID feature. The following pin functions are not available for the Agilex™ 3 FPGA devices: PWRMGT_SDA, PWGMGT_SCL, and PWRMGT_ALERT. Resolution For accurate pin information for the Agilex™ 3 FPGA devices, refer to the Agilex™ 3 FPGA Device Pin-Out Files, which are available from the Pin-Out Files for Altera® FPGAs. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.
Why fcs_client app resulted in page allocation failure and unable to proceed when executing on Agilex™ 5 SoC FPGA Devices?
Description Due to a problem with limited HPS memory resources on the Agilex™ 5 FPGA device (e.g., when deploying it with 1GB RAM or less), kernel memory allocation failures may occur, particularly when invoking crypto services operations via the HPS on a system with fragmented memory. Memory fragmentation can result from repeated crypto services operations, prolonged system uptime, or other workloads that dynamically allocate and free memory. Resolution To work around this problem, consider that the crypto services driver requires 4MB of contiguous memory for each encryption/decryption transaction in the kernel. While tuning parameters such as min_free_kbytes may help by encouraging earlier flushing of buffers or caches, they do not guarantee the reservation of contiguous memory. The Contiguous Memory Allocator (CMA) is enabled in the system, and its reserved size can be increased through kernel boot arguments to improve robustness against fragmentation-related failures. Users and system integrators are responsible for ensuring that the operating system is configured to meet the memory requirements of their expected workloads. Failure to do so may result in degraded performance, application instability, or functional failures.Error (18212): Cannot load final snapshot for partition "root_partition”
Description Due to a problem in Intel® FPGA SDK for OpenCL™ version 19.1, you may see an OpenCL™ kernel compile crash after installing the Intel® Quartus® Prime Software 19.1 0.03 patch. The Intel® FPGA SDK for OpenCL™ uses BAK-cache (a local copy in a temporary folder of the local machine) to speed up subsequent kernel compiles. The error messages are shown below. It should be visible on the standard output and printed in quartus_sh_compile.log. Error (18212): Cannot load final snapshot for partition "root_partition" - the partition is not in a version compatible format. Error: Quartus Prime MIF/HEX Update was unsuccessful. 1 error, 0 warnings Error (23035): Tcl error: Error (23031): Evaluation of Tcl script scripts/post_flow_pr.tcl unsuccessful Resolution There are two ways to work around this problem Approach 1 (Recommended) Delete your local BAK cache. The problem will be solved for the next and all compiles onwards. For Windows, remove $ENV{'USERPROFILE'}\\AppData\\Local\\aocl For Linux, remove /var/tmp/aocl/$ENV{USERNAME} Approach 2 Run “aoc” argument with this option “-no-read-bsp-bak-cache”. Note this will slow down compile by an hour aoc -no-read-bsp-bak-cache <kernel> This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.3.Ubuntu Operating System Support Requires Intel® FPGA Software Version 17.0 Update 1
Description The following publications incorrectly state that Intel® Quartus® Prime Version 17.0 and Intel FPGA SDK for OpenCL™ Version 17.0 provide support for Ubuntu operating systems: Intel Quartus Prime Pro Edition Software and Device Support Release Notes Version 17.0 (RN-01082-17.0.0 published 2017.05.08) Intel Quartus Prime Standard Edition Software and Device Support Release Notes Version 17.0 (RN-01080-17.0 published 2017.05.08) Intel FPGA SDK for OpenCL Version 17.0 Release Notes (RN-OCL004 published 2017.05.08) Ubuntu operating system support requires Version 17.0 Update 1.Installing an unsigned driver might cause an error in the Altera SDK for OpenCL running on Windows 8.1
Description If you run the Altera SDK for OpenCL version 15.1 on Windows 8.1 and you install an unsigned driver, you might encounter the following error messages: difx_install_preinstall_inf: err e000024b, last event 0, last error 0. UNKNOWN difx_install_preinstall_inf: err e000022f, last event 0, last error 0. UNKNOWN Resolution Prior to installing an unsigned driver, disable driver signature enforcement by performing the following steps: On the Windows login screen or under the Charms bar, open the power options menu. Hold the Shift key while you click Restart from the power options menu. After your computer reboots, select the Troubleshoot option. Select Advanced Options. Select Startup Settings. When prompted, click Restart to reboot your computer. When the Startup Settings menu appears, press the F7 key to choose the Disable driver signature enforcement option. After your computer restarts, you can install unsigned drivers.SCDC Values in HDMI Parameter Editor Not Passed Into the HDMI IP Core
Description The values specified for the Manufacturer OUI, Device ID String, and Hardware Revision parameters for the Altera HDMI sink core are not passed into the HDMI sink core properly. As a result, the SCDC registers are not configured properly for these input values. This issue affects all supported devices. Resolution There is no workaround for this issue. This issue is fixed in version 16.0 of the HDMI IP core.Creating OTN_cascade or SDI_cascade Instances at a Low or Medium IP Bandwith Causes the Arria® 10 and Cyclone® 10 GX fPLL or ATX PLL IP Parameter Editor GUI to Encounter an Error Related to f_max_pfd
Description If you set the fPLL or ATX PLL IP bandwidth to low or medium for Arria® 10 and Cyclone® 10 GX devices while attempting to create OTN_cascade or SDI_cascade instances, the IP Parameter GUI might display an error that relates to f_max_pfd. This issue affects the Quartus® Prime Standard Edition Software and the Quartus® Prime Pro Edition Software. Resolution In the fPLL or ATX PLL IP Parameter Editor, you cannot select the bandwidth after you select the OTN or SDI protocol. Therefore, before you create OTN_cascade or SDI_cascade instances, first select Basic from the Protocol mode pull-down menu and then select High from the Bandwith pull-down menu.Why does the Low Latency 100G Ethernet Intel® FPGA IP fail timing on Intel® Stratix® 10 FPGA?
Description When using the Low Latency 100G Ethernet Intel® FPGA IP with RSFEC and/or KR mode enabled on Intel® Stratix® 10 FPGA, timing violations can be observed. Resolution To work around these timing violations when using Intel® Quartus® Prime version 18.0 or 18.1: a. Check the Low Latency 100G Ethernet Intel® FPGA IP placement using the Quartus Prime Chip Planner. If any hard block in the core is in the way of the placement of the Intel® Stratix® 10 100G IP placement, it may create long routing and result in bad timing. If this is the case, please choose a different set of transceiver locations when possible. b. Try seed sweeping to get a better timing result. This problem has been improved but not fixed in version 19.1 of the Intel® Quartus® Prime Edition Software.