Why does the CPRI Intel® FPGA IP Design Example fail to simulate when using the Aldec* Riviera* simulator ?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 and earlier, you might see the CPRI Intel® FPGA IP Design Example fails to simulate when using the Aldec* Riviera* simulator.

Resolution

There is no workaround for this problem.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

Updated 3 months ago

Version 3.0

agilex™ 7 fpgas and socs

arria® 10 fpgas and socs

arria® v fpgas and socs

cyclone® v fpgas and socs

errata

fpga dev tools quartus® prime software standard

stratix® 10 fpgas and socs

stratix® v fpgas

Knowledge Base Article

Why does the CPRI Intel® FPGA IP Design Example fail to simulate when using the Aldec* Riviera* simulator ?

Description

Resolution