Why are the out_valid and out_data of the CIC Intel® FPGA IP stuck at 0 when the "Number of stages" parameter is of a power of 2?

Description

Due to a problem with the CIC Intel® FPGA IP in Intel® Quartus® Prime version 18.1 software, you may observe the above problem if the value of "Number of stages" is of power of 2 and the "Filter type" is Interpolator.

Resolution

There is no workaround for this problem. This problem will be fixed in a future version of the Intel® Quartus® Prime software.

Updated 2 months ago

Version 2.0

arria® 10 fpgas and socs

arria® ii fpgas

arria® v fpgas and socs

cyclone® iv fpgas

cyclone® v fpgas and socs

fpga dev tools quartus® prime software pro

fpga dev tools quartus® prime software standard

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stratix® 10 fpgas and socs

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Knowledge Base Article

Why are the out_valid and out_data of the CIC Intel® FPGA IP stuck at 0 when the "Number of stages" parameter is of a power of 2?

Description

Resolution