Sir, I would like to design a SFPDP module that receive parallel data from F/o module . This is a part of a recorder. My question is how to proceed with Stratix IV board? Can i use ALTGX Transceiver for that? If so please do mention challenges.

Sir,

As you mentioned i done with single channel now, I was able to {Frame, encode,serialize in Transmitter} and{De-serialize, decode, de-frame the data in Receiver} correctly in simulation. But the problem arise when i'm using the hardware setup.

1.I'm using signal tap II analyzer for watching the signal real time

2. There are two FPGA inside my custom board and using one as TX and one as RX

3. I have done the sample code where i was using 8 bit data with control code K28.5

But i'm not able to receive the data properly. How to resolve the problem??

If there is any design example file kindly share here

Thanks in advance

Arya vijayan

Hi,

Sorry for the delay. This case has just been routed to me. As I understand it, you have some inquiries related to using ALTGX XCVR IP. For your information, generally we would address specific inquiry on FPGA but not the design implementation related inquiry. However, I will try my best to advice to my best knowledge.

To ensure we are on the same page, just would like to check with you on the following:

1. Would you mind to further elaborate on your target application with ALTGX? For example, you are trying to feed serial high speed data stream into SIV and would like to use ALTGX to sample and de-serialize it? Some diagram would be helpful for better understanding.
2. What is the data rate and input width of the data input to the SIV devices?
3. Are you using any SIV devkit from Intel?
4. What is the Quartus version that you are using?

Please let me know if there is any concern. Thank you.

Sir, I'm planning to develop an SFPDP IP Core using ALTGX and ALTGX RECONFIG IP's .

Data rate is 650 Mbps

Here i will convert the parallel data from optical to electric module into serial data using the serializing feature of the ALTGX transceiver and also encode the data. After that framing have to be done for signal integrity.

Also the reverse things have to be done in the receiver side

Data is coming in 4 channels each with 16 bit width. Mainly now i'm facing problem in dynamic reconfiguration of ALTGX and ALT RECONFIG and and loop backing of data for testing.

Kindly guide me if i'm wrong

Thank you.

Quartus version 14.0

It is customized dev board with 2 stratix iv FPGA's

Hi,

Thanks for your update. As I checked with the device datasheet, there should be no issue for the SIV XCVR to support the 625Mbps as the min spec is 600Mbps.

I understand that your latest problem is related to ALTGX and ALT_RECONFIG. To ensure we are on the same page, just would like to check with you on the following:

1. Would you mind to further elaborate on the problem observation ie with some screenshots so that I could have a better understanding.

2. You also mentioned about dynamic reconfiguration in your previous note. Generally it is used only if there is a rate change required. Would you mind to help elaborate on why you need reconfiguratioin and the specific issue that you are observing?

3. Just would like to check with you if you are currently observing issue in simulation or hardware? If it is hardware, I would recommend you to start by running Modelsim simulation to isolate out any functional issue before proceed to hardware testing.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

When i was using ALTGX,offset cancellation is automatically enabled and there we need this dynamic reconfiguration right? That's why i have created ALTGX_RECONFIG Instance.

Well, i can summarize my procedure like this

1. By using ALTGX i have developed a transceiver setup with 650 Mbps with 4 channel and 16 bit wide , also the protocol i have used here is XAUI
2. I have a 16 bit input data on each channel and i have to serialize encode and transmit on transmit side
3. Similarly the opposite have to be done in the receiver side of transceiver
4. In between the transmission and reception of data i have to frame and de-frame the data using user logic
5. This whole design is to design SFPDP (Serial front panel data port)

Problems facing

1. Developed the transceiver setup but i'm not able to de-serialize back the serialized output data from the transmitter by loop backing the data in user logic
2. Don't have much idea about dynamic reconfiguration using ALTGX_RECONFIG
3. The explanation available in the user guide is bit confusing

Hi,

Thanks for your elaboration. Please see my responses as following:

1. Regarding the offset cancelllation, yes, your understanding is correct, you would need to connect a ALT_RECONFIG instance to the ALTGX instance in order for the power up offset cancellation to work correctly.

2. The offset cancellation will auto take place one time during device power up. You need to ensure free-running refclk to the ALTGX and reconfig_clk ALT_RECONFIG so that the offset cancellation can be completed successfully.

3. Since you do not require dynamic reconfiguration in your application, you can ignore the dynamic reconfiguration part.

4. I understand that you are running 4 channels and perform test in hardware. To facilitate the debugging and bring up, I would recommend you to start with simple one channel loopback design in Modelsim simulation first. This would be helpful to isolate any functional related issue before moving on to hardware.

5. After the 1 channel design is able to loopback correctly, you can increase to 4 channels per your design and verify again in simulation. Once you are done with simulation, you may then port over to hardware to start validation.

Please feel free to let me know if you encounter any issue during the simulation with 1 channel design.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

Hi,

Just to follow up with you if there is any concern. thank you.

Hi,

Just would like to follow up with you on this. Thank you.

Sir,

I wont be able to show the screenshots, but i can elaborate.

I have designed an sfpdp module using ALTGX ,ALTGX_RECONFIG and created two instance , one for transmitter and one for receiver.

In transmitter side the data is framed using user logic then encoded and serialized using altgx module.

Similarly in receiver side the data serial data is deserialized and decoded using altgx again then deframed using user logic.

I was able to transmit and receive the data in a single fpga using serial loopbacking available in stratix iv dev board.

Then when i used two fpga ( CUSTOM BOARD WHICH CONTAIN 2 STRATIX FPGA'S whose TX and Rx are internally connected) to communicate i was not able to receive the data. May be the data is not synchronizing. how i have to proceed

TOOLS USED: quartus 14.1

modelsim

FPGA: stratix IV( EP4SGX530NF45I3N) ( two fpga, one as TX,RX)

-------------------------------

ALTGX

Protocol : Basic

Data rate: 2.5 GBPS

Input clk freq: 100 MHZ

reconfiguration clk, calibration clock: 50 mhz

OTHERS: enabled 8B/10B encoding, decoding

enabled serializer and deserializer

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