Sir, As you mentioned i done with single channel now, I was able to {Frame, encode,serialize in Transmitter} and{De-serialize, decode, de-frame the data in Receiver} correctly in simulation. But the problem arise when i'm using the hardware setup. 1.I'm using signal tap II analyzer for watching the signal real time2. There are two FPGA inside my custom board and using one as TX and one as RX3. I have done the sample code where i was using 8 bit data with control code K28.5But i'm not able to receive the data properly. How to resolve the problem??If there is any design example file kindly share hereThanks in advanceArya vijayan

Hi, As I understand it, you are sending data between two SIV devices and seems to observe issue at the RX output. Would you mind to further elaborate on the issue observation when you referred to RX unable to received the data correctly? Some screenshots will be helpful for understanding. Thank you. Best regards, Chee Pin

Hi,Sorry for the delay. This case has just been routed to me. As I understand it, you have some inquiries related to using ALTGX XCVR IP. For your information, generally we would address specific inquiry on FPGA but not the design implementation related inquiry. However, I will try my best to advice to my best knowledge.To ensure we are on the same page, just would like to check with you on the following:Would you mind to further elaborate on your target application with ALTGX? For example, you are trying to feed serial high speed data stream into SIV and would like to use ALTGX to sample and de-serialize it? Some diagram would be helpful for better understanding.What is the data rate and input width of the data input to the SIV devices?Are you using any SIV devkit from Intel?What is the Quartus version that you are using?Please let me know if there is any concern. Thank you.

Sir, I'm planning to develop an SFPDP IP Core using ALTGX and ALTGX RECONFIG IP's . Data rate is 650 MbpsHere i will convert the parallel data from optical to electric module into serial data using the serializing feature of the ALTGX transceiver and also encode the data. After that framing have to be done for signal integrity.Also the reverse things have to be done in the receiver sideData is coming in 4 channels each with 16 bit width. Mainly now i'm facing problem in dynamic reconfiguration of ALTGX and ALT RECONFIG and and loop backing of data for testing.Kindly guide me if i'm wrongThank you.

Quartus version 14.0It is customized dev board with 2 stratix iv FPGA's

Forum Discussion

AVija7

New Contributor

6 years ago

Sir, I would like to design a SFPDP module that receive parallel data from F/o module . This is a part of a recorder. My question is how to proceed with Stratix IV board? Can i use ALTGX Transceiver for that? If so please do mention challenges.

Thanks in advance

12 Replies

CheepinC_altera
Regular Contributor
6 years ago
Hi,
thanks for your update. Would you mind to further elaborate on the observation when you refer to "not able to receive the data"? Mind share with me the signaltap of all the ALTGX status signals? This would be helpful to further narrow down what might be wrong.
Thank you.

Forum Discussion

Sir, I would like to design a SFPDP module that receive parallel data from F/o module . This is a part of a recorder. My question is how to proceed with Stratix IV board? Can i use ALTGX Transceiver for that? If so please do mention challenges.

12 Replies

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