Forum Discussion
Sir,
I wont be able to show the screenshots, but i can elaborate.
I have designed an sfpdp module using ALTGX ,ALTGX_RECONFIG and created two instance , one for transmitter and one for receiver.
In transmitter side the data is framed using user logic then encoded and serialized using altgx module.
Similarly in receiver side the data serial data is deserialized and decoded using altgx again then deframed using user logic.
I was able to transmit and receive the data in a single fpga using serial loopbacking available in stratix iv dev board.
Then when i used two fpga ( CUSTOM BOARD WHICH CONTAIN 2 STRATIX FPGA'S whose TX and Rx are internally connected) to communicate i was not able to receive the data. May be the data is not synchronizing. how i have to proceed
TOOLS USED: quartus 14.1
modelsim
FPGA: stratix IV( EP4SGX530NF45I3N) ( two fpga, one as TX,RX)
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ALTGX
Protocol : Basic
Data rate: 2.5 GBPS
Input clk freq: 100 MHZ
reconfiguration clk, calibration clock: 50 mhz
OTHERS: enabled 8B/10B encoding, decoding
enabled serializer and deserializer
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