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Altera_Forum
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14 years ago

Laboratory Exercise 12

Hello,

I need a help to solve the first part of exercise 12, Basic Digital Signal Processing.

I'm using the libraries provided "lab12_design_files."

Insert the following code in the correct area.

--YOUR CODE GOES HERE

process(read_ready, write_ready, read_s, write_s) is

-- Declaration(s)

begin

if (read_ready='1' and read_s='0') then

read_s<='1';

if(write_ready='1' and write_s='0') then

write_s<='1';

writedata_left <= readdata_left;

writedata_right <= readdata_right;

end if;

end if;

read_s<='0';

write_s<='0';

end process;

But the program does not work, does not give errors. But no more sound from the microphone to the speakers.

Thanks,

Filipe Nunes

18 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi, where does "lab12_design_files" come from ? Could you precise more ?

    Your second "if ... end if" might not be nested, I guess.

    You get a process that always gives 

    read_s<='0';
write_s<='0';

    because of the last two lines.:oops:

    So, it is very (very, obviously and drastically) simplified by the compiler/synthesizer

    please review vhdl basics : vhdl is not a programming language:D

    Draw a logic schema on paper first.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hello mmTsuchi.

    Thank you for your help.

    Sorry for my mistakes, but now I started programming in VHDL, so knowledge is not much.

    The file "lab12_design_files," withdrew from the following link:

    "ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Laboratory_Exercises/Digital_Logic/DE2-115/vhdl/"

    I need to get the microphone sound and send it to a column, to apply a filter in the future. I have urgency to solve this problem, which seems basic, but can not solve.

    Without solving this first part, I can not achieve the objective of the work is to apply an FFT filter.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    First, make a schema with logics. (more complex schema needs good writing)

    I guess you want to copy readdata_left to writedataleft and same thing for 'right'

    You might use a synchronous logic (recommended) by using process(clk) because of possible glitches.

    look for "process(clk)" or "synchronous process) even in quartus help

    Something like : 

       process (clock_50)
   begin
      if rising_edge(clock_50) then
          -- not verified at all --
          if(write_ready='1' and write_s='0') then
               write_s<='1';
               writedata_left <= readdata_left;
               writedata_right <= readdata_right;
           end if;
      end if;
   end process;
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hey mates..I have just started to work on Quartus..I have to do this exercise as a part of my course..Can you please guide me on how to approach things?

    I dont have the starterkit kit which is mentioned in the last line of Page 2 on this assignment..I was trying to setup the audio video configs via the SOPC builder..but all to vain..

    I'm terribly disappointed having no tutor to guide on this..Please help if you get time..
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi, please don't make multiple posts.

    I don't know those starter kits but they should give a "prework" which drives you where you can write your code.

    so search for starterkit you mentioned. Else you will probably "burn out" (you have to know pins, to (re)create SOPC system for this exercise, etc )

    you should have a working basic example in what you are been given.

    quartus is a tool which can synthesize and configure fpgas

    vhdl is vhsic hardware description langage (not a programming langage) i suggest you good practice of vhdl (see on altera, doulos...)

    sopc an oether tool integrated with quartus

    nios ii a processor

    Have you tried my code in #5 (http://www.alteraforum.com/forum/showpost.php?p=151641&postcount=4) ?

    PLease could you post the entire file ? (we don't do homeworks for you, but advise you :-))

    EDIT : Sorry for confusing fmvnunes and azonegrpz :oops: :D
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    What is exactly your problem :

    * you have difficulties to write the code. It is quite simple here. I won't answer about that. It is the alphabet of design. If you don't success, change job :-)

    * you get compilation errors

    * no compilation error, but configuration failure

    * success configuring but no working ?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    for someone here: I think we should help each other in this forum, so it will be better if all of us can provide the solution not creating more problem and questions

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    If you give one solution "as is", fmvnunes and lxpool will just copy-and-paste without understanding.

    I guess this exercise is very very very basic (not carefully read the "how to" of the codec). Just make D flip flop (no resample here, just copy input to output). It is the "hello world" of VHDL.

    @azonegrpz : it may be an other problem that we can bring solution.