Laboratory Exercise 12

First, make a schema with logics. (more complex schema needs good writing)

I guess you want to copy readdata_left to writedataleft and same thing for 'right'

You might use a synchronous logic (recommended) by using process(clk) because of possible glitches.

look for "process(clk)" or "synchronous process) even in quartus help

Something like :

   process (clock_50)
   begin
      if rising_edge(clock_50) then
          -- not verified at all --
          if(write_ready='1' and write_s='0') then
               write_s<='1';
               writedata_left <= readdata_left;
               writedata_right <= readdata_right;
           end if;
      end if;
   end process;