Laboratory Exercise 12

Hi, where does "lab12_design_files" come from ? Could you precise more ?

Your second "if ... end if" might not be nested, I guess.

You get a process that always gives

read_s<='0';
write_s<='0';

because of the last two lines.:oops:

So, it is very (very, obviously and drastically) simplified by the compiler/synthesizer

please review vhdl basics : vhdl is not a programming language:D

Draw a logic schema on paper first.