Files seem to be missing from Qsys synthesis of UP entities

Did you install the University Program IP cores? They're a separate download.

http://www.altera.com/education/univ/software/upds/unv-upds.html

Cheers,

Dave

Dave,

In short, yes.

I have a separate directory under C:\altera\11.0sp1\University_Program. There is the Monitor program, Examples, etc. I have been able to load and play with both the Basic Computer and the Media Computer for the DE2-70 board. I have been able to make some minor changes to the Basic Computer. I did that using the SOPC Builder, but was trying to use Qsys, as that seems to be the future.

I have found Qsys somewhat more complex in terms of requiring many more "connections". SOPC Builder seemed to make more interconnects automatically. I am not a "hardware designer", but am trying to develop a simple computer to control a Serial Graphics Display, a DCC model railroad, and incoming XBee communications from the trains. The alternative choice is to use an ATMega 128, but I thought the inherently better built-in I/O on the DE2-70 board would make life easier.

Any other ideas on why this might be failing? I will try to reinstall the UP cores and recompile the project.

Thanks for taking the time to respond.

Regards,

Geof

Dave,

I uninstalled the UP, then completely reinstalled it. No joy. When I instantiate the NIOS processor and compile it fails again with the same error messages.

Regards,

Geof

Dave,

I removed the UP IP's from the Qsys project and used the regular Altera ones. I left out the LCD display, but added the 3 serial ports. It generated the system with 6 warnings and then it compiled.

So who knows. Also FYI the RS232 UP IP core has an error in it. It will not allow the selection of a 19200 baud rate! I was able to recalculate the BAUD_TICK_COUNT, etc to force it to 19200.

Weird.

Geof

Hi Geof,

Sorry to hear the UP cores didn't work. I haven't ever had a need to try them.

Creating a Qsys/SOPC IP core is pretty straight-forward once you get the hang of it. If you create the core yourself, then you're only fixing your own bugs :)

It sounds like you've figured out a work-around that will get you going. If you have trouble figuring out how to get things to work, ask and I'll take a look.

Cheers,

Dave

Thanks, Dave,

I have run into one more issue. I am using the web edition of he Quartus II software. Am I correct is assuming that I cannot use the NIOS processor except on a tethered or time limited basis without a separate license?

That is a real deal breaker for using this approach. My fallback position for using either my DE0-NANO or DE2-70 board is to do everything in Verilog. I am a retired individual and could not justify a great expense for a license.

I appreciate again the time you have spent of this issue. One of the great benefits of forums like this.

Regards,

Geof

PS: with the Cheers signoff are you an Aussie?

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I have run into one more issue. I am using the web edition of he Quartus II software. Am I correct is assuming that I cannot use the NIOS processor except on a tethered or time limited basis without a separate license?

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Use the NIOS II/e core:

http://www.altera.com/devices/processor/nios2/cores/economy/ni2-economy-core.html

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That is a real deal breaker for using this approach. My fallback position for using either my DE0-NANO or DE2-70 board is to do everything in Verilog. I am a retired individual and could not justify a great expense for a license.

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If the NIOS II/e core doesn't work for you, you could try one of the OpenCores cores, eg., OpenRISC or one of the AVR variants, or the Leon SPARC processor. They're all free.

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with the Cheers signoff are you an Aussie?

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Close - NZer (Kiwi) :)

Cheers,

Dave