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Altera_Forum's avatar
Altera_Forum
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13 years ago

Files seem to be missing from Qsys synthesis of UP entities

Gentlemen, I am working on a Qsys project involving the UP 16x2 LCD display and 3 UARTS on a DE2-70 board. The Qsys generation of the NIOS processor works fine with no errors or warnings. However,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Dave,

I removed the UP IP's from the Qsys project and used the regular Altera ones. I left out the LCD display, but added the 3 serial ports. It generated the system with 6 warnings and then it compiled.

So who knows. Also FYI the RS232 UP IP core has an error in it. It will not allow the selection of a 19200 baud rate! I was able to recalculate the BAUD_TICK_COUNT, etc to force it to 19200.

Weird.

Geof