Files seem to be missing from Qsys synthesis of UP entities

Dave,

In short, yes.

I have a separate directory under C:\altera\11.0sp1\University_Program. There is the Monitor program, Examples, etc. I have been able to load and play with both the Basic Computer and the Media Computer for the DE2-70 board. I have been able to make some minor changes to the Basic Computer. I did that using the SOPC Builder, but was trying to use Qsys, as that seems to be the future.

I have found Qsys somewhat more complex in terms of requiring many more "connections". SOPC Builder seemed to make more interconnects automatically. I am not a "hardware designer", but am trying to develop a simple computer to control a Serial Graphics Display, a DCC model railroad, and incoming XBee communications from the trains. The alternative choice is to use an ATMega 128, but I thought the inherently better built-in I/O on the DE2-70 board would make life easier.

Any other ideas on why this might be failing? I will try to reinstall the UP cores and recompile the project.

Thanks for taking the time to respond.

Regards,

Geof