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AnnaK_Altera's avatar
AnnaK_Altera
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2 months ago

Hi Arun,

You can refer to the Agilex 5 HPS Technical Reference Manual: https://www.intel.com/content/www/us/en/docs/programmable/814346/25-3/error-checking-and-correction-controller-93197.html

The EDAC driver documentation also includes a link to the driver source code: https://altera-fpga.github.io/rel-25.3/linux-embedded/drivers/edac/edac/

Check that your kernel includes the memory controller driver and that any ECC config options are enabled. Then ensure your device tree describes ECC-enabled memory regions and controllers. For information on device tree modifications: https://github.com/altera-fpga/agilex5e-ed-gsrd/tree/main/a5ed065es-premium-devkit-oobe/baseline/software/yocto_linux/meta-custom/recipes-bsp/device-tree

  • Arun_Prabakatr's avatar
    Arun_Prabakatr
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    2 months ago

    Hi AnnaK_Altera

    Thanks for the references. We've enabled the EDAC and memory controller drivers in our kernel, and our device tree includes ECC-enabled memory regions.

    Since this is our first time testing ECC on Agilex 5 boards, could you please guide us on how to check if it's working properly? Any steps, tools, or test methods you recommend would be really helpful.