TSE -> SGDMA -> SOC(through f2sdram)

Hello KoenVe,

The root cause was identified.

The active-low reset signal for the F2SDRAM bridge was left unconnected in the top-level design. As a result, Quartus tied the reset signal low and determined that the F2SDRAM bridge was not required. Consequently, the F2SDRAM_RDATA signal became unconnected, leading to the unconnected signal error.

Actual signal is below.

    -- reset signal (no need to synchronize as it is expected that the reset bridge in the Qsys module does the synchronization)
    sReset_n <= sEmif_cal_done_rst_n; -- pFPGA_RESETn & sEmif_local_reset_done;

After tying sReset_n to logic high ('1'), the error no longer occurred.

Lastly, while reviewing the design, I have a few comments.

As described in the user guide below, Platform Designer automatically performs protocol conversion between AXI and Avalon buses, allowing AXI and Avalon interfaces to be connected directly. This conversion includes both bus width adaptation and burst transfer conversion.

Quartus® Prime Pro Edition User Guide

6. Platform Designer Interconnect

https://docs.altera.com/r/docs/683609/26.1/quartus-prime-pro-edition-user-guide/platform-designer-interconnect

Platform Designer allows you to establish connections between Avalon® and AXI interfaces by generating an interconnect logic. This logic enables you to handle the protocol differences. Platform Designer creates the interconnect logic by converting all the protocols to a proprietary packet format. Then, the tool routes the packet through network switches to the appropriate AXI subordinates or Avalon agents. Here, the packet converts to the subordinate's protocol.7

Platform Designer supports Avalon® , AMBA® 3 AXI (version 1.0), AMBA® 4 AXI (version 2.0), AMBA® 4 AXI-Lite (version 2.0), AMBA® 4 AXI-Stream (version 1.0), AMBA ACE5-Lite, and AMBA® 3 APB (version 1.0) interface specifications.

Best regards,

  Yoshiaki