To evaluate and monitor CPU frequency behavior in the Kernel OS

Question

We need to verify CPU frequency behaviour straight from the Linux kernel because we are currently working with a customised Agilex 5 System-on-Module (SOM). Ensuring appropriate frequency scaling and governor functionality under a range of workloads is our aim. Would you kindly provide guidance regarding the device tree modifications, kernel configurations, and testing methods needed to enable and validate CPU frequency scaling on this platform? I would be very grateful for any advice or reference materials that are specific to Agilex 5.

annak_altera · Answer

Hi Arun,In the arm64 config you can see the CPU_FREQ options which will help you implement governor functionality with frequency scaling: https://github.com/altera-fpga/linux-socfpga/blob/socfpga-6.12.33-lts/arch/arm64/configs/defconfigYour kernel will look for operating points in your device tree to set available frequencies. Here is an idea of what the implementation could look like:cpu0: cpu@0 {
    ...
    operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;
    ...
};

...

cpu_opp_table: opp-table {
    compatible = "operating-points-v2";
    opp-1000000000 {
        opp-hz = /bits/ 64 &lt;1000000000&gt;;
        opp-microvolt = &lt;950000&gt;;
    };
    opp-1400000000 {
        opp-hz = /bits/ 64 &lt;1400000000&gt;;
        opp-microvolt = &lt;1050000&gt;;
    };
};After reboot you can use the /sys/devices/system/cpu/cpu0/cpufreq utilities to check available governors, frequencies, and watch how the CPU responds to stress.

arun_prabakatr · Answer

Hi AnnaK_AlteraThanks for the guidance. We've enabled the relevant CONFIG_CPU_FREQ options in our arm64 kernel config and included #include "socfpga_agilex5.dtsi" in our device tree, which contains all the necessary CPU-related nodes including TSC and others.However, after reboot, the /sys/devices/system/cpu/cpu0/cpufreq directory is still not appearing. We've also updated our kernel log file to help identify what might be missing. Could you please take a look and let us know if there's anything we've overlooked?Thanks again for your support.

jamesg_altera · Answer

Hi Arun_Prabakatr,The source of all CPU clocks in an Agilex 5 system on chip is the Clock Manager. You can find some details about it here:https://www.intel.com/content/www/us/en/docs/programmable/814346/25-3/clock-manager.htmlYou will find information about the Linux driver for the Clock Manager here:https://altera-fpga.github.io/rel-25.3/linux-embedded/drivers/clock_manager/clock_manager/

jamesg_altera · Answer

Hi Arun_Prabakatr,Here is some further information on this topic. The Linux driver for clock manager does not support modifying the clock frequency, only reading it. As described in the HPS Technical Reference Manual here...https://www.intel.com/content/www/us/en/docs/programmable/814346/25-3/clock-manager-programming-model.html... there are two supported ways of configuring clock frequencies for the HPS subsystem, including the CPU clocks:Configure in the Parameters section of the HPS IP in Quartus Platform Designer before building the FPGA imageConfigure clock manager register settings in the bootloader, before starting LinuxSection 7.7 of the document goes on to give example register settings for different scenarios. Section 7.8 has details of the relevant registers: https://www.intel.com/content/www/us/en/docs/programmable/814346/25-3/clock-manager-address-map-and-register-49571.htmlIf you find this information helpful, please mark it as the accepted solution.

tiensunga_altera · Answer

JamesG_Altera is 100% correct. Please follow James's suggestion on the UBOOT SSBL to modify the register (ping-pong counter/divider) or Quartus. This is the recommended solution.&nbsp;For the Linux part, I will just add a bit more information. We do not support setting the Clock rate through the clock manager driver in Linux yet. But customers are free to implement it if they want as this is open source. Hence, contributing to the open source community.If you are keen to try, then, i created some basic steps on how to do this in Linux below.&nbsp;Step 1: We need to define the Min, and max frequency or multiple operating frequencies for the CPU cores using the opp-table. I am just giving an example with some sample frequencies. We do not need to specify the operating voltage because the Agilex5 does not support it. We only support frequency scaling. As shown below, you have to add the DT bindings to the clock manager and define the device tree for opp-table. This is not the correct values. And it is only as a demostration.&nbsp;&nbsp;cpus {&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; #address-cells = &lt;1&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; #size-cells = &lt;0&gt;;&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; cpu0: cpu@0 {&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; compatible = "arm,cortex-a55";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; reg = &lt;0x0&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; device_type = "cpu";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; enable-method = "psci";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; next-level-cache = &lt;&amp;L2&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clocks = &lt;&amp;clkmgr AGILEX5_CORE0_FREE_CLK&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clock-names = "cpu";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; operating-points-v2 = &lt;&amp;cpu_opp&gt;; // cpufreq uses these&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; };&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; cpu1: cpu@1 {&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; compatible = "arm,cortex-a55";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; reg = &lt;0x100&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; device_type = "cpu";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; enable-method = "psci";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; next-level-cache = &lt;&amp;L2&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clocks = &lt;&amp;clkmgr AGILEX5_CORE1_FREE_CLK&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clock-names = "cpu";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; operating-points-v2 = &lt;&amp;cpu_opp&gt;; // cpufreq uses these&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; };&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; cpu2: cpu@2 {&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; compatible = "arm,cortex-a76";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; reg = &lt;0x200&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; device_type = "cpu";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; enable-method = "psci";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; next-level-cache = &lt;&amp;L2&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clocks = &lt;&amp;clkmgr AGILEX5_CORE2_FREE_CLK&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clock-names = "cpu";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; operating-points-v2 = &lt;&amp;cpu_opp&gt;; // cpufreq uses these&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; };&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; cpu3: cpu@3 {&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; compatible = "arm,cortex-a76";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; reg = &lt;0x300&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; device_type = "cpu";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; enable-method = "psci";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; next-level-cache = &lt;&amp;L2&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clocks = &lt;&amp;clkmgr AGILEX5_CORE3_FREE_CLK&gt;;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clock-names = "cpu";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; operating-points-v2 = &lt;&amp;cpu_opp&gt;; // cpufreq uses these&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; };&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; cpu_opp: opp-table {&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; compatible = "operating-points-v2";&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; opp-shared;&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; opp-min {&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; opp-hz = /bits/ 64 &lt;10000000&gt;; // 10MHz&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; };&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; opp-max {&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; opp-hz = /bits/ 64 &lt;800000000&gt;;// Example, 800MHz&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; };&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; };&nbsp;Step 2:You have to modify the drivers\clk\socfpga\clk-periph-s10.c to add the 2 ops function for .set_rate and .round_rate. The following codes are just POC and not production quality. The objective is to modify the Ping pong counter. The spec says, that, "Division setting for ping pong counter in clock slice. Divides the core01_clk frequency by this value + 1." The reset value is 0, and the divisor is 1. It will take the maximum frequency of the CPU core.Intel Sundance Mesa HPS Register Map - core01ctr&nbsp;&nbsp;static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,&nbsp; &nbsp; &nbsp; &nbsp; unsigned long parent_rate){&nbsp; &nbsp; &nbsp; &nbsp; struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hw);&nbsp; &nbsp; &nbsp; &nbsp; unsigned long div = 1;&nbsp; &nbsp; &nbsp; &nbsp; if (socfpgaclk-&gt;hw.reg)&nbsp; &nbsp; &nbsp; &nbsp; {&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; /* Calculate divisor */&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; div = (parent_rate/rate) + 1; // We need to obtain the right divisor based on the max clock frequency. The requested rate is assumed to be always smaller than the parent_rate (maximum core frequency)&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; writel(div, socfpgaclk-&gt;hw.reg);&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; pr_err("DEBUG: clk_cpu_set_rate %d parent= %d, divisor = %d
", rate, parent_rate, div);&nbsp; &nbsp; &nbsp; &nbsp; }&nbsp; &nbsp; &nbsp; &nbsp; return clk_peri_cnt_clk_recalc_rate(hw, parent_rate);}&nbsp;// This is not implemented in full yet. Just for demo.static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,&nbsp; &nbsp; &nbsp; &nbsp; unsigned long *parent_rate){&nbsp; &nbsp; &nbsp; &nbsp; return rate;}static const struct clk_ops peri_cnt_clk_ops = {&nbsp; &nbsp; &nbsp; &nbsp; .recalc_rate = clk_peri_cnt_clk_recalc_rate,&nbsp; &nbsp; &nbsp; &nbsp; .get_parent = clk_periclk_get_parent,&nbsp; &nbsp; &nbsp; &nbsp; .set_rate = clk_cpu_set_rate,&nbsp; // &lt;- Define the new function here&nbsp; &nbsp; &nbsp; &nbsp; .round_rate = clk_cpu_round_rate // Define the new function here.};&nbsp;Testing the solution. You should be able to see cpufreq once you have both Device tree and Device driver (clock manager) hacked.You must set the governor to user-space in order for you to modify the cpu frequency from sysFS.root@dhcp0:~# echo userspace &gt; /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor&nbsp;&nbsp;Modify the speed (in kHz)echo 50000 &gt; &nbsp;/sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed&nbsp;root@dhcp0:~# ls /sys/devices/system/cpu/cpu0/cpufreq &nbsp;affected_cpus &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; related_cpus &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; scaling_governorcpuinfo_cur_freq &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;scaling_available_frequencies &nbsp;scaling_max_freqcpuinfo_max_freq &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;scaling_available_governors &nbsp; &nbsp;scaling_min_freqcpuinfo_min_freq &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;scaling_cur_freq &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; scaling_setspeedcpuinfo_transition_latency &nbsp;scaling_driver &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; stats

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To evaluate and monitor CPU frequency behavior in the Kernel OS

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