New Contributor
New ContributorHi Arun,
In the arm64 config you can see the CPU_FREQ options which will help you implement governor functionality with frequency scaling: https://github.com/altera-fpga/linux-socfpga/blob/socfpga-6.12.33-lts/arch/arm64/configs/defconfig
Your kernel will look for operating points in your device tree to set available frequencies. Here is an idea of what the implementation could look like:
cpu0: cpu@0 {
...
operating-points-v2 = <&cpu_opp_table>;
...
};
...
cpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <950000>;
};
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1050000>;
};
};After reboot you can use the /sys/devices/system/cpu/cpu0/cpufreq utilities to check available governors, frequencies, and watch how the CPU responds to stress.
New ContributorHi AnnaK_Altera
Thanks for the guidance. We've enabled the relevant CONFIG_CPU_FREQ options in our arm64 kernel config and included #include "socfpga_agilex5.dtsi" in our device tree, which contains all the necessary CPU-related nodes including TSC and others.
However, after reboot, the /sys/devices/system/cpu/cpu0/cpufreq directory is still not appearing. We've also updated our kernel log file to help identify what might be missing. Could you please take a look and let us know if there's anything we've overlooked?
Thanks again for your support.
New ContributorHi Arun_Prabakatr,
The source of all CPU clocks in an Agilex 5 system on chip is the Clock Manager. You can find some details about it here:
https://www.intel.com/content/www/us/en/docs/programmable/814346/25-3/clock-manager.html
You will find information about the Linux driver for the Clock Manager here:
https://altera-fpga.github.io/rel-25.3/linux-embedded/drivers/clock_manager/clock_manager/
New ContributorHi Arun_Prabakatr,
Here is some further information on this topic. The Linux driver for clock manager does not support modifying the clock frequency, only reading it. As described in the HPS Technical Reference Manual here...
https://www.intel.com/content/www/us/en/docs/programmable/814346/25-3/clock-manager-programming-model.html
... there are two supported ways of configuring clock frequencies for the HPS subsystem, including the CPU clocks:
Section 7.7 of the document goes on to give example register settings for different scenarios. Section 7.8 has details of the relevant registers: https://www.intel.com/content/www/us/en/docs/programmable/814346/25-3/clock-manager-address-map-and-register-49571.html
If you find this information helpful, please mark it as the accepted solution.
