Arria 10 HPS - DMA EMAC reset issue

Hello,

We found the root cause and resolved the issue.

The problem was that the PLL in the FPGA GMII-to-SGMII clock path was not locked. As a result, the required clocks supplied to the HPS EMAC were not valid, and the DMA software reset bit remained asserted:

DMA_BUS_MODE.SWR = 1

This behavior matches the Arria 10 documentation:

When using the FPGA GMII/MII interface, you must have a stable RX clock (emac_clk_rx_i) and TX clock (emac_clk_tx_i) supplied from the PHY to the EMAC before bringing the EMAC out of reset.

The register description for DMA_BUS_MODE.SWR also states that the bit is cleared automatically only after the reset operation has completed in all active GMAC clock domains. Therefore, all PHY input clocks required by the selected interface must be present for the software reset to complete.

In our case, the PLL lock condition could not be determined through the available HPS registers. We were only able to identify the issue using Signal Tap.

To verify the clock path, the FPGA firmware team implemented a counter driven by the relevant clock. The counter showed that the expected clock was not running, which confirmed that the PLL had not locked.

After fixing the PLL configuration and verifying that the clocks were active and stable, the SWR bit cleared successfully and the Ethernet interface started working.

Thank you for the guidance. The recommendation to verify emac_clk_rx_i and emac_clk_tx_i using Signal Tap helped us identify the root cause.