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Derek_Teng's avatar
Derek_Teng
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5 months ago
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Questions about the descriptors of the Modular Scatter - Gather DMA Core

Hi, When I was reading the "Modular Scatter - Gather DMA Core" chapter in the book "Embedded Peripherals IP User Guide", there is a part that I'm not particularly clear about. I'm not sure if my understanding is correct, so I'd like to ask for advice. In the Modular Scatter - Gather DMA Core, when I don't enable the Prefetcher Core, can I write multiple descriptors into the dispatcher FIFO through the Descriptor Agent Port at once? Then, by setting the Go bit in the Control Field of the last descriptor to 1 and starting the DMA transfer, the DMA transfer will process the multiple descriptors I just input in sequence. If this operation is feasible, I think that even without enabling the Prefetcher Core, the same function as the descriptor list can be achieved.

Pcie
  • KelvinK_Altera's avatar
    KelvinK_Altera
    5 months ago

    Hi Derek,

    @Derek_Teng wrote:

    In the Modular Scatter - Gather DMA Core, when I don't enable the Prefetcher Core, can I write multiple descriptors into the dispatcher FIFO through the Descriptor Agent Port at once? Then, by setting the Go bit in the Control Field of the last descriptor to 1 and starting the DMA transt input in sequence.

    You are right.

    Yours use case do not required the following prefetcher features, you can don't enable prefetcher.

    With Prefetcher enabled, following features are supported:

    • Descriptor linked list
    • Data transfer to non-contiguous memory space
    • Descriptor write back
    • Hardware descriptor polling
    • 64-bit address spaces

9 Replies

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    5 months ago

    Hi


    I will now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Regards

    Jingyang , Teh


  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    5 months ago

    Hi


    Sorry I am not really familiar with this IP as it is part of the PCIE solution.

    Would I suggest you to recreate a new post regarding the new question on the Avalon-MM DMA IP.


    Regards

    Jingyang, Teh


    • Derek_Teng's avatar
      Derek_Teng
      Icon for New Contributor rankNew Contributor
      5 months ago

      Okay, thank you for your suggestion. I'll initiate a new post.

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    5 months ago

    Hi


    The msgdma do not support out of order description completion.

    The out of order completion mentioned is within the burst feature, it is confined within the descriptor.

    The current descriptor is completed before the next descriptor is being processed.


    Regards

    Jingyang, Teh


    • Derek_Teng's avatar
      Derek_Teng
      Icon for New Contributor rankNew Contributor
      5 months ago

      Hi, Jingyang,

      Sorry, my question is no longer about MSGDMA, but about the Avalon-MM DMA IP core described in the document "Arria ® 10 or Cyclone ® 10 GX Avalon ® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide".
      The issue of out-of-order completion is related to this IP core. Please help me check if my understanding is correct.

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    5 months ago

    Hi


    The out of order mentioned here is when a single large read is split into multiple smaller read request.

    The smaller read request could be handled at an "out-of-order" behavior.

    Completion is send once all smaller read request is completed but it is in order of request.


    Regards

    Jingyang, Teh


    • Derek_Teng's avatar
      Derek_Teng
      Icon for New Contributor rankNew Contributor
      5 months ago

      Hi Jingyang，

      My understanding is that, assuming there are 128 descriptors in the scatter-gather descriptor list of a DMA transfer, after dma_rd_master reads back these 128 descriptors, the DMA controller may not necessarily execute these descriptors in order？
      Or, the DMA controller executes these descriptors in order, but due to bus or system reasons, the completion times of each descriptor may not be in order.
      Assume that these 128 descriptors are read descriptors, that is, reading data from the FPGA and writing it to the system memory.
      Then, in the timing of dma_wr_master, the change of the read address should be incremental (it will not execute the read operation of descriptor 2 first and then that of descriptor 1). That is to say, dma_wr_master reads data from the RAM in ascending order of addresses.
      When the read data is forwarded to the system memory, since the completion times of each TLP transfer are out of order, the completion of each descriptor is also out of order in terms of time and not completed in sequence.
      I'm not sure if my understanding is correct.

  • KelvinK_Altera's avatar
    KelvinK_Altera
    Icon for New Contributor rankNew Contributor
    5 months ago

    Hi Derek,

    @Derek_Teng wrote:

    In the Modular Scatter - Gather DMA Core, when I don't enable the Prefetcher Core, can I write multiple descriptors into the dispatcher FIFO through the Descriptor Agent Port at once? Then, by setting the Go bit in the Control Field of the last descriptor to 1 and starting the DMA transt input in sequence.

    You are right.

    Yours use case do not required the following prefetcher features, you can don't enable prefetcher.

    With Prefetcher enabled, following features are supported:

    • Descriptor linked list
    • Data transfer to non-contiguous memory space
    • Descriptor write back
    • Hardware descriptor polling
    • 64-bit address spaces
    • Derek_Teng's avatar
      Derek_Teng
      Icon for New Contributor rankNew Contributor
      5 months ago

      Thank you for your reply.
      I have another question regarding the Avalon-MM DMA IP core. The document "Arria ® 10 or Cyclone ® 10 GX Avalon ® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide" states that the DMA supports out-of-order completion.
      This means that if I have 128 descriptors, the 128th descriptor may be completed before the 127th descriptor.
      May I ask if I can turn off this out-of-order completion feature? I don't want it to complete the descriptors out of order. Instead, I hope it can complete each descriptor in sequence.