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Derek_Teng's avatar
Derek_Teng
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5 months ago
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Questions about the descriptors of the Modular Scatter - Gather DMA Core

Hi, When I was reading the "Modular Scatter - Gather DMA Core" chapter in the book "Embedded Peripherals IP User Guide", there is a part that I'm not particularly clear about. I'm not sure if my unde...
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  • KelvinK_Altera's avatar
    KelvinK_Altera
    5 months ago

    Hi Derek,

    @Derek_Teng wrote:

    In the Modular Scatter - Gather DMA Core, when I don't enable the Prefetcher Core, can I write multiple descriptors into the dispatcher FIFO through the Descriptor Agent Port at once? Then, by setting the Go bit in the Control Field of the last descriptor to 1 and starting the DMA transt input in sequence.

    You are right.

    Yours use case do not required the following prefetcher features, you can don't enable prefetcher.

    With Prefetcher enabled, following features are supported:

    • Descriptor linked list
    • Data transfer to non-contiguous memory space
    • Descriptor write back
    • Hardware descriptor polling
    • 64-bit address spaces
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
5 months ago

Hi


The out of order mentioned here is when a single large read is split into multiple smaller read request.

The smaller read request could be handled at an "out-of-order" behavior.

Completion is send once all smaller read request is completed but it is in order of request.


Regards

Jingyang, Teh


Derek_Teng's avatar
Derek_Teng
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5 months ago

Hi Jingyang，

My understanding is that, assuming there are 128 descriptors in the scatter-gather descriptor list of a DMA transfer, after dma_rd_master reads back these 128 descriptors, the DMA controller may not necessarily execute these descriptors in order？
Or, the DMA controller executes these descriptors in order, but due to bus or system reasons, the completion times of each descriptor may not be in order.
Assume that these 128 descriptors are read descriptors, that is, reading data from the FPGA and writing it to the system memory.
Then, in the timing of dma_wr_master, the change of the read address should be incremental (it will not execute the read operation of descriptor 2 first and then that of descriptor 1). That is to say, dma_wr_master reads data from the RAM in ascending order of addresses.
When the read data is forwarded to the system memory, since the completion times of each TLP transfer are out of order, the completion of each descriptor is also out of order in terms of time and not completed in sequence.
I'm not sure if my understanding is correct.