Derek_Teng
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Question about TXS interface of the PCIe IP core (AVMM) for Cyclone 10 GX
Hi Regarding the txs_address_i[w-1:0] of the TXS interface of the PCIe IP core (AVMM) for Cyclone 10 GX, the user manual states: "Address of the read or write request from the external Avalon-MM master. This address translates to 64-bit or 32-bit PCI Express addresses based on the translation table. The value is determined when the system is created." In addition, it also states: "Note: The PCI Express-to-Avalon-MM bridge supports both 32- and 64-bit addresses. If you select 64-bit addressing the bridge does not perform address translation." When I instantiate the PCIe IP core and set the Avalon-MM address width to 64-bit, the parameters "Number of address pages" and "Size of address pages" will not appear. Instead, there is "Address width of accessible PCIe memory space". The value of w in txs_address_i[w-1:0] is equal to the value of the parameter "Address width of accessible PCIe memory space". My questions are: When I choose to set the Avalon-MM address width to 64-bit, is the address on txs_address_i equal to the address of the PCIe domain to be accessed? If so, do I need to set the "Address width of accessible PCIe memory space" to 64? If I don't set it to 64, then txs_address_i cannot cover the 64-bit address. If the PCIe core does not perform address translation, how can it obtain the 64-bit PCIe domain address through this address that is less than 64 bits? In addition, it should be noted that my PCIe address is 64-bit.Solved1.3KViews0likes1CommentRe: Questions about the descriptors of the Modular Scatter - Gather DMA Core
Hi, Jingyang, Sorry, my question is no longer about MSGDMA, but about the Avalon-MM DMA IP core described in the document "Arria ® 10 or Cyclone ® 10 GX Avalon ® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide". The issue of out-of-order completion is related to this IP core. Please help me check if my understanding is correct.2.4KViews0likes0CommentsRe: Questions about the descriptors of the Modular Scatter - Gather DMA Core
Hi Jingyang， My understanding is that, assuming there are 128 descriptors in the scatter-gather descriptor list of a DMA transfer, after dma_rd_master reads back these 128 descriptors, the DMA controller may not necessarily execute these descriptors in order？ Or, the DMA controller executes these descriptors in order, but due to bus or system reasons, the completion times of each descriptor may not be in order. Assume that these 128 descriptors are read descriptors, that is, reading data from the FPGA and writing it to the system memory. Then, in the timing of dma_wr_master, the change of the read address should be incremental (it will not execute the read operation of descriptor 2 first and then that of descriptor 1). That is to say, dma_wr_master reads data from the RAM in ascending order of addresses. When the read data is forwarded to the system memory, since the completion times of each TLP transfer are out of order, the completion of each descriptor is also out of order in terms of time and not completed in sequence. I'm not sure if my understanding is correct.2.6KViews0likes0CommentsRe: Two questions regarding the Avalon-MM DMA IP core
Thank you very much for your reply. I think I've found a way to deal with out-of-order completion. Since the data I need to read is input sequentially, when the DMA controller executes descriptors out-of-order, it's very likely that when the 127th descriptor is executed, the data read actually belongs to the 1st descriptor. So I have to place two RAMs. After one RAM is filled with a certain amount of data, say 16KB, the computer initiates a DMA transfer. Even if the dma_wr_master reads this RAM out-of-order, there's no need to worry that the data the computer gets is in a mess. The two RAMs perform ping-pong operations, enabling rapid data provision during multiple DMA transfers. By the way, will the BAR0 of this IP core occupy 512 bytes of space?750Views0likes0CommentsTwo questions regarding the Avalon-MM DMA IP core
Hi, I have two questions regarding the Avalon-MM DMA IP core: 1. The document 《Arria ® 10 or Cyclone ® 10 GX Avalon ® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide》 states that the DMA supports out-of-order completion. This means that if I have 128 descriptors, the 128th descriptor might be completed before the 1st descriptor. May I ask if I can turn off this out-of-order completion feature? Can I make it complete each descriptor in order? 2. Regarding the RXM0 interface in this IP core, the document mentions that “The receive path from the RXM_BAR0 connects internally. It is not shown in the connections panel.” When writing the driver program, I need to know the addressing range of BAR0. However, I can't find relevant information in the documentation, nor can I obtain its addressing range in the qsys project. May I ask what the addressing range of BAR0 in this IP core is?Solved857Views0likes3CommentsRe: Questions about the descriptors of the Modular Scatter - Gather DMA Core
Thank you for your reply. I have another question regarding the Avalon-MM DMA IP core. The document "Arria ® 10 or Cyclone ® 10 GX Avalon ® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide" states that the DMA supports out-of-order completion. This means that if I have 128 descriptors, the 128th descriptor may be completed before the 127th descriptor. May I ask if I can turn off this out-of-order completion feature? I don't want it to complete the descriptors out of order. Instead, I hope it can complete each descriptor in sequence.2.9KViews0likes0CommentsQuestions about the descriptors of the Modular Scatter - Gather DMA Core
Hi, When I was reading the "Modular Scatter - Gather DMA Core" chapter in the book "Embedded Peripherals IP User Guide", there is a part that I'm not particularly clear about. I'm not sure if my understanding is correct, so I'd like to ask for advice. In the Modular Scatter - Gather DMA Core, when I don't enable the Prefetcher Core, can I write multiple descriptors into the dispatcher FIFO through the Descriptor Agent Port at once? Then, by setting the Go bit in the Control Field of the last descriptor to 1 and starting the DMA transfer, the DMA transfer will process the multiple descriptors I just input in sequence. If this operation is feasible, I think that even without enabling the Prefetcher Core, the same function as the descriptor list can be achieved.Solved3.1KViews0likes9CommentsRe: PCIe design reference recommendation (Cyclone 10 GX)
Thank you. I think I've found a better solution. I use the generic component in the IP column of the platform designer to create my own interface module. It's very convenient to export the RXM interface, the data source interface for DMA write operations, and the data output interface for DMA read operations to my external logic. At the same time, I can also adjust its address allocation so that the address addressing range meets my design requirements and matches well with the addressing space on the computer side. Thank you!3KViews1like2Comments