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IOzan's avatar
IOzan
Icon for Occasional Contributor rankOccasional Contributor
1 day ago

Preloader/U-Boot Compilation Failure

General Background: 

I'm working with a custom board that has an Altera/Intel Cyclone V, SoC FPGA (5CSEBA6U23, similar to the DE10-Nano development kit). The board is already equipped with all the necessary files for a successful boot sequence from a uSD card (FPGA and the ARM processor (HPS)).

The Objective:

I want to reconfigure the HPS functionality (Mux) for pins 53 and 54 from their current GPIO to CAN BUS. I need to ensure a successful boot from the uSD card with the updated hardware definition and Device Tree.

Issue Description: Preloader/U-Boot Compilation Failure

After successfully implementing the changes in Quartus and Platform Designer and after successfully generating the BSP files (bsp-editor), I'm attempting to run the "make" command to build the Preloader/U-Boot image. The process starts and creates the uboot-socfpga directory, but the compilation consistently fails with several errors, and the final boot image is not updated.

Extension of the successfully completed steps:

  1. I've modified the Platform Designer (Qsys) mux functionality to reconfigure the HPS peripheral pins (GPIO53-GPIO54) for CAN BUS functionality.
  2. I've integrated the new HPS component into the top-level VHDL project.
  3. I've Generate a full VHDL compilation in Quartus.
  4. Using the "SoC EDS Command Shell", I launched the BSP-Editor and loaded the updated "settings.bsp" file. After generation, the "hps_isw_handoff" and "generated" directories were updated.
  5. I have manually verified the output files (pinmux_config.h) to confirms that CAN1 is now correctly configured in the pin multiplexing settings.

What should I do?  

 

3 Replies

  • IOzan's avatar
    IOzan
    Icon for Occasional Contributor rankOccasional Contributor

    First, thank you very much for your quick response!

     

    Below are the software versions I'm using on my standalone laptop:

    • Quartus Prime: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
    • SoC EDS Command Shell: Version 18.1 [Build 625]

     

    Note One (From the log file)

    According to the log file, the system initially searches for the file uboot-socfpga.tar.gz inside the intelFPGA/18.1 installation directory. This is strange because I'm working with the lite vision… I moved the file into the project directory and updated the Makefile accordingly which resulted in the rest of the log entries as shown in the attached file.

     

    Note: I have a second computer (network license) with the following version:

    • Quartus Prime: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition

    However, that machine does not have the SoC EDS installed.

    Would it be helpful if I purchased additional add-ons for the internal network computer and performed the process there instead? Do you think that would resolve the issue? If so, what add-ons should i purchase? What can I do to continue the process in my stand alone lite computer? 

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor

    Hi IOzan ,

    On top of Sho comments, could you also tell us also about the software version that you're using (eg. uboot, Quartus etc) ?

     

    Thanks.

    Regards

    Kian

  • ShoH_Altera's avatar
    ShoH_Altera
    Icon for Occasional Contributor rankOccasional Contributor

    Hi IOzan​ ,

    Could you let me know which version of the tool you are using?
    Also, could you share the log text from the make command—including the exact error messages you are seeing?

    Thank you,
    Sho