mmc blocks written = error

Hi,

Apologies for the delay reply as I saw that there is already a duplicate thread on the same issue

https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/How-to-access-the-8GB-ram-of-DDR-in-Agilex-7/td-p/1660123/page/2

Been discussing with my colleague on the cases and he mentioned that we will use the other thread to follow up. May I know whether can set this thread to community support and we will use the other thread to continue on the debugging.

Thanks

Regards

Kian

Hi Gokulraj,

Sorry for the delay in getting back, was checking with our factory apps on this.

Apparently this is a known issue as there is another case with similar issue, quote from the other case findings

1. MMU table missing the mapping for higher memory bank, and the issue only being seen with dcache turn on, as this would trigger MMU run, and when MPU access those memory region not defined in MMU table mapping would causing system hang
2. With logical block enable, the default logic memory layout would set reserve to higher memory region, hence any feature like sf, tftp and wget which calling lmb check would prevent MPU to access higher memory region

I've attached the Patches.zip file here but it is based on the latest build thus might not be compatible if you're running an older version of the code.

You can try to manually edit the files indicated here (add in those in green) and rebuild uboot fsbl and itb (or you can refer to the patches on the changes)

Thanks

Regards

Kian

Hi Gokulraj,

Thanks for using Altera Forums, I'm Kian and will be looking into this case. Let me check on this issue and revert to you later.

Thanks

Regards

Kian