New ContributorFPGA digital image processing project. DE1SOC
Hello, hope everyone is doing fine.
I am facing a problem with a digital image processing project that I am currently implementing on the DE1SOC FPGA.
My proposed architecture is a generation of ROWS x COLS of a 1-bit input/output cell which will perform the digital image processing on the input image (the cells are connected together in hardware). (My hardware involves shift registers and other components).
So i am trying to make an interface between the FPGA and the HPS (ARM-9).
My plan is, for example if i have a 5x5 image in C, i want to send 1 bit of each element/pixel from the HPS to the fpga every single cycle ( of course we need handshaking between the fpga and the hps in that case), and then after a number of cycles i want to also receive the data bit by bit and store them into an array as integers.
The de1soc has an heavyweight AXI-bus which can send 128bits at once.
so i was thinking if its possible to send 128 bits to my design ( which each bit of the 128 is actually 1 bit of an 8bit pixel, so in other words ill be sending 1 bit from each of the 128 pixels (8times), and then receive them the same way 1 bit at a time and store them in a new array).
