Central1New Contributor3 years agoFPGA digital image processing project. DE1SOC Hello, hope everyone is doing fine. I am facing a problem with a digital image processing project that I am currently implementing on the DE1SOC FPGA. My proposed architecture is a generation of ...Show More
Recent DiscussionsNeed Step-by-Step Guide: Configuring Arria 10 HPS for UART0 Access (Tools & Workflow)A topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected.SolvedU-Boot "Synchronous Abort" boot failure on Terasic Atum A5 Rev B via Quartus 24.3 .jic generationAgilex7m i have configure 4GB ddr linux is not booting. I got architect time failure error.Preloader/U-Boot Compilation Failure