FPGA digital image processing project. DE1SOC

Hello, thanks for the reply!

I think, my explanation in the thread was not really clear. Sorry, I don't have that huge experience with FPGA's so I am going to explain what I want to do using some sketches I made.

Okay so in the following sketch as you can see;

I want to use the full power of the heavy-weight* AXI-BUS (128bits). Basically ill be sending 128 bits to my design, but each bit of the 128 is going to be sent to a cell of the 128 cells.

The cell I made is serial so it has 1-bit I/O's (includes shift registers and other extc).

ill be sending to each cell a pixel (8-bits), so i will be repeating the process i made below 8 times. in order to fill the reg in the cell.

ill be doing it as the following: 1 bit at once to assure speed and efficiency.

Now technically, that was the easy part. the harder part now is the following :

that's the hard part, doing the thing from the HPS side. this must be done as shown for inputting the image and also when i want to receive the image.

Thanks in advance!