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Central1
New Contributor
New ContributorFPGA digital image processing project. DE1SOC
Hello, hope everyone is doing fine.
I am facing a problem with a digital image processing project that I am currently implementing on the DE1SOC FPGA.
My proposed architecture is a generation of ...
EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
If you're trying to use only 1 bit out of the 128 bit of the AXI bridge, it's not really practical.
Can you take a look at this example see if this is similar on what you're trying to achieve?:
