Forum Discussion

New Contributor

4 years ago

FPGA digital image processing project. DE1SOC

Hello, hope everyone is doing fine. I am facing a problem with a digital image processing project that I am currently implementing on the DE1SOC FPGA. My proposed architecture is a generation of ...

EBERLAZARE_I_Intel

Regular Contributor

4 years ago

Hi,

If you're trying to use only 1 bit out of the 128 bit of the AXI bridge, it's not really practical.

Can you take a look at this example see if this is similar on what you're trying to achieve?:

https://ftp.intel.com/Public/Pub/fpgaup/pub/Teaching_Materials/current/Tutorials/Intel_FPGA_Monitor_Program_ARM.pdf

Forum Discussion

FPGA digital image processing project. DE1SOC

Recent Discussions

Unique ID registers in Cyclone V

Audio interface with Agilex 5 A5ED065BB32AI4S

Operating system kernel-level FPGA bridge communication

Routing PL DDR to PS

Validating ECC Functionality on Custom Agilex 5 SOM in Linux Kernel