New ContributorCyclone V DDR3 SDRAM timing configuration missing in handoff files
My query relates to SDRAM timing and skew parameters modified in platform designer that (after generation, FPGA rebuild and create BSL script) do not appear in the handoff files.
We have a PCB with a Cyclone V SoC FPGA (5CSXFC6C6U23I7) and the HPS interfacing to a single 4Gb DDR3 SDRAM device (EltronTech EM6HE16EWAKG). We are using the uboot SPL as the preloader (v2021.10).
On running the preloader SDRAM calibration fails at the calibration write stage. So we assume there is some issue with the skew between CK and DQS. The CK traces are slightly shorter than DQS, with CK about 20 ps shorter).
To address this, we have tried to adjust some of the SDRAM board skew settings in Platform Designer. We then successfully run generate HDL, then rebuild the FPGA and programming files to produce HPS handoff files, execute the create BSL script, rebuild and execute uboot SPL, there is no change observed in the debug output (debug level 2 is enabled in sequencer.c).
Indeed, the handoff files are identical across SDRAM timing changes.
On inspection, it appears that only a subset of the SDRAM timing parameters make it into the emif.pre.cml and sdram_config.h files (tMRD, tRAS, tRCD, tRP, tREFI, tRFC, tWR, tWTR, tFAW, tRRD and tRTP).
My questions are:
- What happens to the other settings such as tDQSCK and the board skew parameters such as Maximum CK delay to DIMM, Maximum DQS delay to DIMM, Max and Min delay difference between CK and DQS, etc?
- Are they set in the SDRAM controller somehow? Should they be - is this even possible?
- What should be done to ensure these parameters are used?
- Failing the above, is there some other way to make timing adjustments to ensure successful SDRAM calibration?
I've added screenshots of the platform designer SDRAM timing settings forms and sdram_config.h for reference.
