Cyclone V DDR3 SDRAM timing configuration missing in handoff files

Hi Jingyang,

We have since found the cause of the SDRAM failing to complete calibration: an error in the PCB layout has the SDRAM BA1 and BA0 swapped between the Cyclone V and the SDRAM chip. As a result, the commands for the SDRAM mode registers 1 and 2 will also be swapped. As it doesn't look possible for the bank address pins to be reassigned in software, the crossed signals have been corrected by a hardware modification to the tracks (on inner PCB layers, so not easy!) and the SDRAM now completes successfully.

It would still be interesting to know whether SDRAM board skew and other SDRAM timing settings made in Platform Designer are used by the HPS.

Peter