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PeterTs's avatar
PeterTs
Icon for New Contributor rankNew Contributor
2 years ago

Cyclone V DDR3 SDRAM timing configuration missing in handoff files

My query relates to SDRAM timing and skew parameters modified in platform designer that (after generation, FPGA rebuild and create BSL script) do not appear in the handoff files. We have a PCB with ...
Hps Boot
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Peter



Glad that your problem is solved.

The values of the Platform Designer is used by the HPS through the handoff files.


The values of the platform designers are exported as an xml files in the "hps_isw_handoff\soc_system_hps_0" in the quartus project folder.

Then while building the bootloader we will need to run a script which is the "cv_bsp_generator.py script".

This script will generate a few header files in which is used to compiled together with the bootloader.


https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Boot_from_SD_Card


Regards

Jingyang, Teh