Forum Discussion
Custom board on Cyclone V HPS SDRAM preloader test
Dear Intel and all,
Apart from the DDR3 topology.
The first stage testing shows a very puzzling behavior.
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 488 KHz
CLOCK: QSPI clock 2343 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
SDRAM: Ensuring specified SDRAM size is correct ...failed
The final result is that even with a fly-by routed topology there are no issue on both 1.5V and 1.35V DDR3 DDR3L.
The MT41K128M16 /w 1k page size shows no sanity issue on memtest stresapptest on distro.
UBOOT memory normal test also passed w/o any errors.
So after short testing we can only assume there are inherent bug on Quartus 18.1? or HPS IP.
No matter it is /w or /wo the board settings no drop no crash no stuck.
So the case ends here.
18 Replies
- tehjingy_Altera
Regular Contributor
Hi
What SDRAM Size that you are using?
Did you define the correct SDRAM size in the device tree as the sdram installed on the board?
Regards
Jingyang, Teh
- BrianSune_Froum
Contributor
New data
If I do in purposed and messed up the DLL of the DDR and force it to run 25MHz 256x16 is able to pass the test and even run the distro normally.
If I just remain the lower byte of the remain MT41K25616 DDR die it can pass the startup test as well and run 300MHz on C8 speed grade.
How could this even possible when lower byte can work but not both lower and upper byte?
Please do help - BrianSune_Froum
Contributor
I think this is caused by the fly-by routing.
There are two mt41k256m16.
But even I disassembled the far end die it is still not working properly.
Do there any way I can reduce the clock to 250M or 200M for sanity test?
I am so puzzling that with a 8 layer board on fly-by 50ohm and 100ohm design sill can't make things work?