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BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
5 months ago
Solved

Custom board on Cyclone V HPS SDRAM preloader test

Dear Intel and all, Apart from the DDR3 topology. The first stage testing shows a very puzzling behavior. BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 50000 KHz CLOCK: EOSC2 clock...
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  • BrianSune_Froum's avatar
    BrianSune_Froum
    4 months ago

    The final result is that even with a fly-by routed topology there are no issue on both 1.5V and 1.35V DDR3 DDR3L.
    The MT41K128M16 /w 1k page size shows no sanity issue on memtest stresapptest on distro.
    UBOOT memory normal test also passed w/o any errors.

    So after short testing we can only assume there are inherent bug on Quartus 18.1? or HPS IP.

    No matter it is /w or /wo the board settings no drop no crash no stuck.

    So the case ends here.

tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
5 months ago

Hi


What SDRAM Size that you are using?

Did you define the correct SDRAM size in the device tree as the sdram installed on the board?


Regards

Jingyang, Teh


BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
5 months ago

@JingyangTeh_Altera

New data

If I do in purposed and messed up the DLL of the DDR and force it to run 25MHz 256x16 is able to pass the test and even run the distro normally.

If I just remain the lower byte of the remain MT41K25616 DDR die it can pass the startup test as well and run 300MHz on C8 speed grade.

How could this even possible when lower byte can work but not both lower and upper byte?

Please do help