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BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
1 year ago
Solved

Custom board on Cyclone V HPS SDRAM preloader test

Dear Intel and all, Apart from the DDR3 topology. The first stage testing shows a very puzzling behavior. BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 50000 KHz CLOCK: EOSC2 clock...
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  • BrianSune_Froum's avatar
    BrianSune_Froum
    1 year ago

    The final result is that even with a fly-by routed topology there are no issue on both 1.5V and 1.35V DDR3 DDR3L.
    The MT41K128M16 /w 1k page size shows no sanity issue on memtest stresapptest on distro.
    UBOOT memory normal test also passed w/o any errors.

    So after short testing we can only assume there are inherent bug on Quartus 18.1? or HPS IP.

    No matter it is /w or /wo the board settings no drop no crash no stuck.

    So the case ends here.

tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi


What SDRAM Size that you are using?

Did you define the correct SDRAM size in the device tree as the sdram installed on the board?


Regards

Jingyang, Teh


BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
1 year ago

@JingyangTeh_Altera

I think this is caused by the fly-by routing.

There are two mt41k256m16.
But even I disassembled the far end die it is still not working properly.

Do there any way I can reduce the clock to 250M or 200M for sanity test?

I am so puzzling that with a 8 layer board on fly-by 50ohm and 100ohm design sill can't make things work?