Arria 10 SoC FPGA Remote update via HPS/linux

Hi aik,

I'm using the standard U-boot code from official Intel repository https://github.com/altera-opensource/u-boot-socfpga ,

I've seen in socfpga_common.h that there is a specific script for programming the core https://github.com/altera-opensource/u-boot-socfpga/blob/61ae22e548ebda525d5216d107e45f20eca70537/include/configs/socfpga_common.h#L193-L194

so I the fpga core is correctly loaded. The problem is in force reloading the peripheral bitstream.

Is there a way to force FPGA programming at every reboot? Maybe changing some code in preloader functions here? https://github.com/altera-opensource/u-boot-socfpga/blob/61ae22e548ebda525d5216d107e45f20eca70537/arch/arm/mach-socfpga/spl_a10.c#L114-L150

Or maybe it is better to make a step back and perform the full FPGA programming in SPL at every reboot instead in half in SPL and half in TPL?

Regards.

Hi Aik,

sorry for the delay: I've checked out the Early I/O Release and the checkboxes are selected both in "device options" of quartus and also in qsys. Let me try a little bit more next week so I will come to you with extensive trials: I will try also to change the code of the preloader.

Regards.

Hi Aik,

I've checked again the early I/O release, both in quartus and in qsys. Results are attached.

This is a screenshot of the console during booting, so it seems that early I/O are configured correctly.

I've prepared two .its files with two different bistreams (inside every .itb file there is the periph/core .rbf pair) and I confirm that only rebooting the board via linux does not trigger FPGA reconfiguration. Only a power cycle triggers the correct reconfiguration with the new .itb file. Probably the preloader is checking only the flags is_fpgamgr_user_mode and is_fpgamgr_early_user_mode.

So from now I will try to modify the code of spl_a10.c file. Is it correct to modify only the spl_board_init() function or I need to check other files in the preloader?

Hi aik,

I have some news: I modified the spl_board_init() function in spl_a10.c, changing the following lines (https://github.com/altera-opensource/u-boot-socfpga/blob/61ae22e548ebda525d5216d107e45f20eca70537/arch/arm/mach-socfpga/spl_a10.c#L126-L152) from that:

	/* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
	if (is_fpgamgr_user_mode()) {
		ret = config_pins(gd->fdt_blob, "shared");

		if (ret)
			return;

		ret = config_pins(gd->fdt_blob, "fpga");
		if (ret)
			return;
	} else if (!is_fpgamgr_early_user_mode()) {
		/* Program IOSSM(early IO release) or full FPGA */
		fpgamgr_program(buf, FPGA_BUFSIZ, 0);

		/* Skipping double program for combined RBF */
		if (!is_fpgamgr_user_mode()) {
			/*
			 * Expect FPGA entered early user mode, so
			 * the flag is set to re-program IOSSM
			 */
			force_periph_program(true);

			/* Re-program IOSSM to stabilize IO system */
			fpgamgr_program(buf, FPGA_BUFSIZ, 0);
			force_periph_program(false);
		}
	}

to this:

	/* If the full FPGA is already loaded, force re-program (needed for reboot) */
	if (is_fpgamgr_user_mode()) {
		
		force_periph_program(true);
		fpgamgr_program(buf, FPGA_BUFSIZ, 0);
		fpgamgr_program(buf, FPGA_BUFSIZ, 0);
		force_periph_program(false);

	} else if (!is_fpgamgr_early_user_mode()) {
		/* Program IOSSM(early IO release) or full FPGA */
		fpgamgr_program(buf, FPGA_BUFSIZ, 0);

		/* Skipping double program for combined RBF */
		if (!is_fpgamgr_user_mode()) {
			/*
			 * Expect FPGA entered early user mode, so
			 * the flag is set to re-program IOSSM
			 */
			force_periph_program(true);

			/* Re-program IOSSM to stabilize IO system */
			fpgamgr_program(buf, FPGA_BUFSIZ, 0);
			force_periph_program(false);
		}
	}

So, in the first if I'm checking the FPGA status: since the boot is forced to SD/MMC card in my application, the FPGA can't be already loaded. This will break the compatibility with EPCQ load but in our case is not needed. Then, if it is in user mode, a reboot has been issued, forcing the reprogram. About this, I have a question: is the double programming needed for stability as suggested in the else condition below? Or a single reprogram of the peripherals is enough?

Regards.