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GBraj's avatar
GBraj
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Arria 10 SoC FPGA Remote update via HPS/linux

Hello everybody, we are using an Intel Arria 10 SX with HPS on a custom board (10AS057K4F40E3SG with Quartus Pro 22.4). The boot flow is as specified on Rocketboards website (https://www.rocketboar...
  • aikeu's avatar
    aikeu
    3 years ago

    Hi GBraj,


    Double config can solve the some issue related DDR issue in A10. So it will be required.


    Thanks.

    Regards,

    Aik Eu


aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi GBraj,


Probably can try to modify the code to force it to reload FPGA bit stream by taking out the if (is_fpgamgr_user_mode()) condition when spl_board_init().

Anyway just wanto confirm that referring to this document AN 860: Using Intel® Arria® 10 SoC FPGA Early I/O Release, page 9

https://cdrdv2-public.intel.com/667022/an-a10-soc-fpga-early-io-release-683437-667022.pdf

Did you enable the early IO release in your qsys design?


Thanks.

Regards,

Aik Eu