Arria 10 SoC FPGA Remote update via HPS/linux

Hi Aik,

I've checked again the early I/O release, both in quartus and in qsys. Results are attached.

This is a screenshot of the console during booting, so it seems that early I/O are configured correctly.

I've prepared two .its files with two different bistreams (inside every .itb file there is the periph/core .rbf pair) and I confirm that only rebooting the board via linux does not trigger FPGA reconfiguration. Only a power cycle triggers the correct reconfiguration with the new .itb file. Probably the preloader is checking only the flags is_fpgamgr_user_mode and is_fpgamgr_early_user_mode.

So from now I will try to modify the code of spl_a10.c file. Is it correct to modify only the spl_board_init() function or I need to check other files in the preloader?