Forum Discussion
New ContributorArria 10 SoC FPGA Remote update via HPS/linux
Regular ContributorHi GBraj,
When in U-boot, did you try to perform the below before perform reboot in linux kernel?
setenv coreaddr 0x1000000
load mmc 0:1 ${loadaddr} fit_spl_fpga.itb
imxtract ${loadaddr} fpga-core-1 ${coreaddr}
fpga load 0 ${coreaddr} ${filesize}
Thanks.
Regards,
Aik Eu
GBrajHi aik,
I'm using the standard U-boot code from official Intel repository https://github.com/altera-opensource/u-boot-socfpga ,
I've seen in socfpga_common.h that there is a specific script for programming the core https://github.com/altera-opensource/u-boot-socfpga/blob/61ae22e548ebda525d5216d107e45f20eca70537/include/configs/socfpga_common.h#L193-L194
so I the fpga core is correctly loaded. The problem is in force reloading the peripheral bitstream.
Is there a way to force FPGA programming at every reboot? Maybe changing some code in preloader functions here? https://github.com/altera-opensource/u-boot-socfpga/blob/61ae22e548ebda525d5216d107e45f20eca70537/arch/arm/mach-socfpga/spl_a10.c#L114-L150
Or maybe it is better to make a step back and perform the full FPGA programming in SPL at every reboot instead in half in SPL and half in TPL?
Regards.
