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K606
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11 months ago
Solved

Agilex 5 EMAC to EMAC : Driver error

I am trying to ping one EMAC from another, and have instantiated the following in the HPS: These are exported to the top level, then connected as followed: // https://www.intel.com/content/...
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  • K606's avatar
    K606
    10 months ago

    Solved: bring MAC signals up a module

K606's avatar
K606
Icon for Contributor rankContributor
11 months ago

Hi @TiensungA_Altera ,

In terms of the clocking setup - I am currently doing the following:

- Feeding the output 1/2.5G port of MAC-0 to the input 1/2.5G port of MAC-1

- Feeding a custom 25MHz clock generated in the Fabric to the 10/100M ports of each MAC

I notice that in the HPS editor, there are these fields:

Which is confusing, as it makes me wonder why there is the extra option here (also documented here as not used in 1/2.5G

input  wire        emac0_mac_tx_clk_i_wire,     // not used in 1/2.5 Gbps
When exporting the EMAC interface from Qsys to the top level design.
However - it is not clear from this error report how the signal should in fact be connected to avoid such an error.

I have shared the relevant bitstreams here

Many thanks,

K

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