Forum Discussion
Occasional ContributorA topic explaining a problem with Cyclone V SoC - u-booting .rbf file failure - got rejected.
Hello Yoshiaki,
Thank you so much for taking the effort to test the .rbf files I built and shared on your own DE10-Nano system, and confirming them that they actually work. :)
On my side, on my own QMTECH board, I did the check (performed the register read from U-Boot shell) of the 'stat' register of the FPGA Manager Module, and I think I found my answer/reason for my troubles. So I had set MSEL SW to '01010' (ON-OFF-ON-OFF-ON) on my board, stopped at U-Boot, issued the command and got the below:
=> md ff706000 1 ff706000: 00000058 X... =>So, I do NOT get the expected: 'ff706000: 00000050 P...' , but actually 'ff706000: 00000058 X...' . And then I checked my board physically , toggling one pin at a time , and then reading back the 'stat' register after each pin change. And it was found out that one of the pad pins (the PIN.5) of the DIP SW was broken. And toggling the one switch adjacent to that pin, made no change in the 'stat' register readout.
So, I think the cause had been found for why Uboot can't load compressed .rbf succesfully - my board has a broken MSEL DIP SW pin and it just physically cannot apply/provide the MSEL = '01010'. So, I have to fix my board in this case.
Anyway, at this point, I think the issue is to be considered SOLVED. You can close this ticket.
Much gratitutes Yoshiaki, you've been of great help!
Best Regards,
- Monk M.
Occasional ContributorHi, here's an update:
I've tried again to generate compressed bitstream files (.rbf) and then feed it - to be loaded by UBoot, during boot-up. At the beginning, I took the uncrompressed .sof file created when building the Quartus HW project, and then used the 'Convert Programming Files...' tool , to convert and compress the .sof file into .rbf file, using the following settings:
And then used the created .rbf file to create a bootable and SD Card .img file. And then set the MSEL [4:0] switches = '00010' and '00110' , according to the table:
And then I tried all kinds of combinations , including the ones you posted:
Mode | MSEL | Compression | POR Delay |
FPPx16 | 00010 | Enabled | Fast |
FPPx32 | 01010 | Enabled | Fast |
FPPx16 | 00110 | Enabled | Standard |
FPPx32 | 01110 | Enabled | Standar |
And still , when booting the image, I get the ' Command 'load' failed: Error -6' error , when Uboot is loading the .rbf file. :(
What I am supposed to do here, to get compressed FPGA configs to be booted? I am lost.... (I've attached a .zip file, containng my .sof, .rbf and .cof files used).
Note: The board that I am using is a (QMTECH Cyclone V SoC board) clone of Terasic's DE10-Nano, so the provided (attached here) .rbf file is to be compatible with the Terasic's board. The .rbf file contains the hw design of the DE10-Nano GHRD project, from the provided Demo Projects by Terasic. So nothing special.
Occasional ContributorHello monkstein88,
Thank you for testing .rbf again.
We have verified .rbf with/without compress mode on Cyclone V SoC DevKit.
Please double check of MSEL setting.
Accdoring to QMTECH_Cyclone_V_SoC_KFB_Dual_SDRAM_Schematic_20240607_V01.pdf,
Please keep in mind to set SW5 for MSEL to ON to represent 0 and to OFF to represent 1.
Next , here are commands to generate .rbf from .sof.
quartus_cpf -c -o bitstream_compression=on soc_system.sof soc_system_comp_on.rbf
quartus_cpf -c -o bitstream_compression=off soc_system.sof soc_system_comp_off.rbfHere are actual logs on Cyclone V SoC Dev Kit.
In case of MSEL = 01000 (FPPx32, Compress Off, Fast)
U-Boot SPL 2025.07-g35abb4f1cedc-dirty (May 18 2026 - 13:18:14 +0900)
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 578 ms
Trying to boot from MMC1
U-Boot 2025.07-g35abb4f1cedc-dirty (May 18 2026 - 13:18:14 +0900)
CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC Internal Transceiver (3.0V)
DRAM: 1 GiB
Core: 33 devices, 18 uclasses, devicetree: separate
MMC: dwmmc0@ff704000: 0
Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Warning: ethernet@ff702000 (eth0) using random MAC address - 4e:4c:9a:70:2d:81
eth0: ethernet@ff702000
Hit any key to stop autoboot: 0
=> load mmc 0:1 ${loadaddr} soc_system_comp_on.rbf
2356140 bytes read in 120 ms (18.7 MiB/s)
=> fpga load 0 ${fileaddr} $filesize
Command 'load' failed: Error -6
=> load mmc 0:1 ${loadaddr} soc_system_comp_off.rbf
7007204 bytes read in 351 ms (19 MiB/s)
=> fpga load 0 ${fileaddr} $filesize
=>In case of MSEL = 01010 (FPPx32, Compress ON, Fast)
U-Boot SPL 2025.07-g35abb4f1cedc-dirty (May 18 2026 - 13:18:14 +0900)
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 579 ms
Trying to boot from MMC1
U-Boot 2025.07-g35abb4f1cedc-dirty (May 18 2026 - 13:18:14 +0900)
CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC Internal Transceiver (3.0V)
DRAM: 1 GiB
Core: 33 devices, 18 uclasses, devicetree: separate
MMC: dwmmc0@ff704000: 0
Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Warning: ethernet@ff702000 (eth0) using random MAC address - 1e:b9:e6:16:1a:1c
eth0: ethernet@ff702000
Hit any key to stop autoboot: 0
=> load mmc 0:1 ${loadaddr} soc_system_comp_on.rbf
2356140 bytes read in 120 ms (18.7 MiB/s)
=> fpga load 0 ${fileaddr} $filesize
=> load mmc 0:1 ${loadaddr} soc_system_comp_off.rbf
7007204 bytes read in 351 ms (19 MiB/s)
=> fpga load 0 ${fileaddr} $filesize
Command 'load' failed: Error -6
=>Lastly, please upload your .sof file.
Best regards,
Yoshiaki Saito
- monkstein88
Hi Yoshiaki,
Darn, I forgot to attach my files earlier. Anyway, here they are now - check the 'soc_system_files.zip'. I have the uncompressed .sof, uncompressed .rbf , the compressed .rbf utilizing the .cof file. Also I put my .qsf file for additional info. Thanks for continue to look into this, I just wonder do you have a Terasic DE10-Nano board, somewhere around you to test? In addition, I've attached a zip of my .img file that I use to write to my SD Card and boot on my board - it features the compressed .rbf file, that fails to load properly on my board.
FYI, I am aware of the MSEL settings for the board :
- but whatever DIP SW combination I try, I always get this error -6 :(
Hope this helps. :/
- YoshiakiS_Altera
Hello monkstein88,
Thank you for sharing the photo with us.
Accdoring to a part of QMTECH_Cyclone_V_SoC_KFB_Dual_SDRAM_Schematic_20240607_V01.pdf below ,
MSEL order is opposite compared to your photo.
Here are pin assignments for MSEL.
SW5.1:MSEL0
SW5.2:MSEL1
SW5.3:MSEL2
SW5.4:MSEL3
SW5.5:MSEL4
Best regards,
Yoshiaki Saito
- monkstein88
Hi again,
Well, the photo is taken directly from QMTECH's github repo: https://github.com/ChinaQMTECH/QMTECH_Cyclone_V_SoC_KFB_With_Dual_SDRAM/blob/main/QMTECH_Cyclone_V_SoC_KFB_with_Dual_SDRAM_How_to.pdf
Which could be depicting a wrong MSEL layout, but , as I said I tried different combinations of MSEL DIP SW settings - with different reading/treating the bit positions regarding MSEL [4:0] . So I tried treating/counting from the pin 5 side as MSEL[0] . Then when that didn't work, tried with treating/counting from the pin 1 side as MSEL[0]. And that didn't work either.
And with both readings/side representations - I've tried all kind of MSEL combinations and nothing worked with the compressed .rbf - that I provided in the .zip of my previous post.
At this point I am lost, something is not right, but I can't figure out what :(
I just start to thing if my UBoot is not broken - even though it can load uncompressed .rbf. Or something is wrong the way I create the .rbf.
:/
