New ContributorWrong syntax highlighting in editor when using "define" in Verilog
Hi
Switching from Quartus Prime Standard 19 to >=20 I found out that the syntax highlighting is not working correctly any more in the editor if a definition statement is given in a different file. I'm using Verilog.
For instance:
File 1 "switches.sv" :
`define USETHIS
File 2 "main.sv" :
module test1
(
input clk,
input reset
);
`ifdef USETHIS
wire one;
`else
wire two;
`endif
[..]
endmodule
Both files are in the same hierarchy and folder.
The compiler uses "wire one" as expected but the editor highlights "wire two" ignoring the definition. Only if I put " `define USETHIS " into file 2 the editor interpretes it and highlights the correct line.
Is there any new setting that I missed out - or is this a bug?
Thank you for the feedback provided on this issue.
The engineering team has aware of this issue and they will plan to fix this. (usually will takes some time e.g. a couple of months before it got fix in the next Quartus release.)
Since this issue will be planned to be fixed, do you need further help in this case?
Regards,
Richard Tan
