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JoeLUH's avatar
JoeLUH
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Wrong syntax highlighting in editor when using "define" in Verilog

Hi Switching from Quartus Prime Standard 19 to >=20 I found out that the syntax highlighting is not working correctly any more in the editor if a definition statement is given in a different file. ...
  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    Thank you for the feedback provided on this issue.

    The engineering team has aware of this issue and they will plan to fix this. (usually will takes some time e.g. a couple of months before it got fix in the next Quartus release.)

    Since this issue will be planned to be fixed, do you need further help in this case?


    Regards,

    Richard Tan


RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

I checked 19.1, 20.1, 21.1 and 22.1, it seems to be a GUI issue. I will report this to the engineering team.

You still able to compile the design even if the syntax is not highlighted, right?

Best Regards,

Richard Tan

JoeLUH's avatar
JoeLUH
Icon for New Contributor rankNew Contributor
3 years ago

Yes, exactly. It does compile correctly when setting the switches. Can be tested with the line "force_error" in my above sample code.

Best regards,
Joe