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JoeLUH's avatar
JoeLUH
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Wrong syntax highlighting in editor when using "define" in Verilog

Hi Switching from Quartus Prime Standard 19 to >=20 I found out that the syntax highlighting is not working correctly any more in the editor if a definition statement is given in a different file. ...
  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    Thank you for the feedback provided on this issue.

    The engineering team has aware of this issue and they will plan to fix this. (usually will takes some time e.g. a couple of months before it got fix in the next Quartus release.)

    Since this issue will be planned to be fixed, do you need further help in this case?


    Regards,

    Richard Tan


RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Yes, please use the older version for now.

With that, I will now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.