Forum Discussion
Wrong syntax highlighting in editor when using "define" in Verilog
- 3 years ago
Thank you for the feedback provided on this issue.
The engineering team has aware of this issue and they will plan to fix this. (usually will takes some time e.g. a couple of months before it got fix in the next Quartus release.)
Since this issue will be planned to be fixed, do you need further help in this case?
Regards,
Richard Tan
Do you mean like color highlighting to indicate keywords? (A screenshot might work better here.) Had you run analysis & elaboration at least? There's no way a file would know anything about what's in another file in the project until you at least run A&E. If you're saying this is still incorrect after a full compilation, then yeah that may be a bug.
- JoeLUH3 years ago
New Contributor
Hi sstrell,
yes, that concerns the keywords and also // comments .
These are the two files as visible in editor after full compilation, behaviour is described in the sources:
Since I'm generally using numerous switches in my projects, this bug (if it is a bug) makes my all source codes unreadable for me - so I'm forced to go back to older versions.
I'm wondering if some others have detected and described this, since it appears since version 21 or 20 (not sure right now). I've been seeking for that but haven't found anything.
Could it be reported somewhere?