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Altera_Forum's avatar
Altera_Forum
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14 years ago

Wrong answer when calling component

I'm having a big problem. I'm in this over 10 hours and can't fix it.

I have a project that works fine. But I want to call it as a component inside other project.

I'm sure that the right values are going to the component, but it returns me the wrong answer. And if I test it individually with the same values it returns the right answer.

Maybe when working with arrays is different tha way to call a component?

Does someone knows some possible reason to that?

I didn't put the part of the code where the array "sinal_entrada_a" receives the values, but I tested and I'm sure it have the right numbers. 


LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE matrizes IS
TYPE array_t IS ARRAY (0 TO 7, 0 to 7) OF STD_LOGIC_VECTOR(0 TO 7);
TYPE array_t2 IS ARRAY (0 TO 7, 0 to 7) OF STD_LOGIC_VECTOR(0 TO 11);
END matrizes;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.matrizes.all;
ENTITY rct_512 IS
PORT (
clk: IN STD_LOGIC;
entrada: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saida: OUT array_t2
);
END rct_512;
ARCHITECTURE comportamento OF rct_512 IS
signal sinal_entrada_a: array_t;
COMPONENT rct IS
PORT (
clk: IN STD_LOGIC;
entrada: IN array_t;
saida: OUT array_t2
);
END COMPONENT;
BEGIN
label_10: rct PORT MAP (clk, sinal_entrada_a, saida);
END comportamento;

Thank you very much!

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    There's nothing special with the construct - as far as shown. How do you test it?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    To make sure the "sinal_entrada_a" have the right numbers, I've comented the component label_10, changed the "saida" to array_t and write the line:

    saida <= sinal_entrada_a;

    So I proved checking the simulator that sinal_entrada_a have the right numbers.

    If you fell necessary, here's the full code. 

    
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE matrizes IS
TYPE array_t IS ARRAY (0 TO 7, 0 to 7) OF STD_LOGIC_VECTOR(0 TO 7);
TYPE array_t2 IS ARRAY (0 TO 7, 0 to 7) OF STD_LOGIC_VECTOR(0 TO 11);
TYPE array_t3 IS ARRAY (0 TO 7, 0 to 7) OF STD_LOGIC_VECTOR(0 TO 14);
TYPE array_t4 IS ARRAY (0 TO 15, 0 to 15) OF STD_LOGIC_VECTOR(0 TO 7);
END matrizes;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.matrizes.all;
ENTITY rct_512 IS
PORT (
clk: IN STD_LOGIC;
entrada: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
saida: OUT array_t2
);
END rct_512;
ARCHITECTURE comportamento OF rct_512 IS
------------------------------------------
----------------SIGNAL--------------------
SIGNAL sinal_entrada: array_t4;
signal sinal_entrada_a: array_t;
SIGNAL clk_var: integer range 0 to 256 :=0;
SIGNAL i, ii: integer range 0 to 15 :=0; 
signal done: std_logic:='0';
-------------------END--------------------
COMPONENT rct IS
PORT (
clk: IN STD_LOGIC;
entrada: IN array_t;
saida: OUT array_t2
);
END COMPONENT;
BEGIN
--------------Import Entrada serial mode----
Process (clk)
Begin
    if clk'event AND (clk='1') then
    if done='0' then
        if clk_var=256 then done<='1'; end if;
            if clk_var<256 then
        
            clk_var<=clk_var+1;                        
            sinal_entrada(i, ii)<=entrada;
            ii<=ii+1;
        
                    if (ii=15) then
                    i<=i+1;
                    ii<=0;
                    end if;            
        end if;
        
            else    ------take 8x8 matrix from sinal_entrada
        
                for i in 0 to 7 loop
                    for j in 0 to 7 loop
                        sinal_entrada_a(i, j) <= sinal_entrada(i, j);
                    end loop;
                end loop;        
       end if;
    end if;
end process;
--saida <= sinal_entrada_a;
label_10: rct PORT MAP (clk, sinal_entrada_a, saida);
END comportamento;
    The "if" part is a little confusing but is working. It intend to import 256 bytes (16x16 matrix) from "entrada" via serial.

    And the "else" part is to take the first 8x8 block from the matrix after all the samples is imported. That 8x8 block is the input of the component.

    Thank You!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Your post still doesn't say, how you test the code. With a simulator, either Modelsim or Quartus 9 internal simulator, you are able to trace internal signals and see, what's the problem.

    Personally I don't like, that the input data processing (demultiplexing of entrada) is started on it's own without an external synchronization. This gives room for sync faults.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I'm using the Quartus 9 internal simulator.

    I've created two Matlab programs, one that generates a input *.vec file that I open on the simulator tool. And other to read the *.tbl answer, but just for these quick tests, when I want to see just if one or two answers are right, I am just grouping a few answers on the simulator.

    This is the input file i'm using, quartus is reading that fine.

    This file tells the clk to change every 5ns, with a period of 10ns.

    and change the input "entrada" to the next number every 10ns.

    The entrada samples goes up to 256 lines (16x16). 

    START 0;
STOP 10000;
INTERVAL 5;
INPUTS clk ;
PATTERN
0
1 ;
INTERVAL 10;
INPUTS entrada entrada entrada entrada entrada entrada entrada entrada;
PATTERN
0 1 1 1 1 1 1 0
1 1 1 1 1 1 0 1
0 1 0 0 1 1 1 1
1 0 0 0 1 0 0 0
1 1 0 0 0 0 1 0
0 0 1 1 1 1 1 1
1 0 1 1 0 1 0 0
1 1 0 1 0 1 1 1
0 0 0 1 0 1 1 1
0 0 0 0 0 0 1 1
1 1 0 0 0 0 0 0
0 0 1 0 1 0 1 1
0 0 0 1 1 0 0 0
0 0 1 0 0 1 0 1
1 1 0 0 1 1 1 0
1 0 1 0 0 1 0 0
.
.
.

    I'm using virtual pins as i/o on the component, since there are too many pins. That is still synthesizable, right?

    Hope I answer your questions.

    Thank you!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I'm using virtual pins as i/o on the component, since there are too many pins. That is still synthesizable, right?

    --- Quote End ---

    Yes in that it will tell you how many resources are used in this design.

    No if you want to actually run in on a chip. Virtual pins are just that - virtual. They have no connection to the outside world so you have no way to get any input or output to them.

    Also, the internal simulator only simulates synthesised designs. You would be much better off doing an RTL simulation in Modelsim, as you can more easily debug your code and trace the signals through your design.

    PS. Quartus 10+ has no internal simulator.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I thought that when used as a component virtual pins would work, since I don't really need the pins, it's just a signal.

    There is some way I could have a component with lets say 2000 in/out?

    Also, any tips where I can find some content about how is done image processing, decomposing it on 8x8 blocks, etc?

    I will download and start with Modelsim.

    Thank you!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I thought that when used as a component virtual pins would work, since I don't really need the pins, it's just a signal.

    There is some way I could have a component with lets say 2000 in/out?

    --- Quote End ---

    No. Not even the biggest most expensive devices have that many IO pins!

    You will have to look into some data transport protocall to get data in or out of your system (like ethernet, or serial).
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Ok, thanks.

    If I needed to call just one or two times the component, I could put the content of the component directly on the code. But I will need to call it too many times.

    I will think in some ways I could put data in/out a component via serial.

    Thank you!