Wrong answer when calling component

I'm using the Quartus 9 internal simulator.

I've created two Matlab programs, one that generates a input *.vec file that I open on the simulator tool. And other to read the *.tbl answer, but just for these quick tests, when I want to see just if one or two answers are right, I am just grouping a few answers on the simulator.

This is the input file i'm using, quartus is reading that fine.

This file tells the clk to change every 5ns, with a period of 10ns.

and change the input "entrada" to the next number every 10ns.

The entrada samples goes up to 256 lines (16x16).

START 0;
STOP 10000;
INTERVAL 5;
INPUTS clk ;
PATTERN
0
1 ;
INTERVAL 10;
INPUTS entrada entrada entrada entrada entrada entrada entrada entrada;
PATTERN
0 1 1 1 1 1 1 0
1 1 1 1 1 1 0 1
0 1 0 0 1 1 1 1
1 0 0 0 1 0 0 0
1 1 0 0 0 0 1 0
0 0 1 1 1 1 1 1
1 0 1 1 0 1 0 0
1 1 0 1 0 1 1 1
0 0 0 1 0 1 1 1
0 0 0 0 0 0 1 1
1 1 0 0 0 0 0 0
0 0 1 0 1 0 1 1
0 0 0 1 1 0 0 0
0 0 1 0 0 1 0 1
1 1 0 0 1 1 1 0
1 0 1 0 0 1 0 0
.
.
.

I'm using virtual pins as i/o on the component, since there are too many pins. That is still synthesizable, right?

Hope I answer your questions.

Thank you!